CN-122002788-A - Dynamic random access memory and manufacturing method thereof

CN122002788ACN 122002788 ACN122002788 ACN 122002788ACN-122002788-A

Abstract

The dynamic random access memory comprises a substrate, an array area and a peripheral area, an active area, a word line structure, a bit line side wall, an isolation structure, a node contact plug, a storage node and a landing pad, wherein the array area is provided with the array area, the active area is arranged in the array area in an array mode and penetrates through the active area, the bit line structure is arranged in the array area and comprises a bit line electrode structure arranged on the active area, the bit line side wall comprises a first side wall and a bit line electrode structure, a bit line protection layer is arranged between the second side wall and the bit line electrode structure, the bit line protection layer is arranged on the side surface of the bit line side wall, the isolation structure is arranged between the node contact plug and the bit line structure at intervals, the node contact plug is connected with the active area, the landing pad is partially arranged on the node contact plug and is partially arranged on the bit line structure, the storage node is arranged on the landing pad, the peripheral area comprises a peripheral cover layer and covers the circuit structure, the upper surface of the second side wall is lower than the upper surface of the first side wall and the bit line protection layer, and the bit line protection layer is arranged between the upper surface of the second side wall and the landing pad.

Inventors

Shi luan
CHEN YINCHU
ZHU SHUN
FANG KE
XU YIJIA
SUN YAO

Assignees

长鑫科技集团股份有限公司

Dates

Publication Date: 20260508
Application Date: 20241105

Claims (10)

1. A method for manufacturing a dynamic random access memory is characterized in that, Providing a substrate, wherein the substrate is provided with an array region and a peripheral region, the array region is provided with an active region which is arranged in an array manner, a word line structure is arranged in the substrate and penetrates through the active region, a bit line structure is arranged in the array region and is in contact with the active region, the bit line structure comprises a bit line electrode structure, a bit line side wall and a bit line covering layer, the bit line electrode structure is formed on the active region, the bit line side wall comprises a first side wall and a second side wall, the first side wall is formed between the second side wall and the bit line electrode structure, the bit line covering layer covers the side surface and the upper surface of the bit line side wall and the upper surface of the bit line electrode structure, an isolation structure, a first sacrificial member, the first sacrificial member and the isolation structure are formed between the bit line structure at intervals, a second connecting member, and the second connecting member is formed on at least part of the bit line structure and the first sacrificial member on two sides of the bit line structure, the peripheral covering layer comprises a circuit covering layer, the peripheral region comprises a circuit covering layer, the peripheral covering layer covers the circuit covering layer and the peripheral covering layer; Removing the protective layer, the second connecting piece and part of the bit line covering layer to expose the second side wall; removing at least part of the second side wall to form a gap and the first sacrificial member to form a node groove; forming a reinforcing layer which covers the side surface and the upper surface of the bit line structure and at least fills part of the gap; Forming a node contact plug, wherein the node contact plug at least fills part of the node groove; forming a landing pad partially formed in the node trench in contact with the node contact plug and partially formed on the bit line structure; A storage node is formed, the storage node being formed on the landing pad.
2. The method for manufacturing the dynamic random access memory according to claim 1, it is characterized in that the method comprises the steps of, And removing the protective layer, the second connecting piece and part of the bit line covering layer to expose the second side wall, wherein the protective layer, the second connecting piece and part of the bit line covering layer are removed simultaneously through a first removing process to expose the second side wall.
3. The method for manufacturing the dynamic random access memory according to claim 1, it is characterized in that the method comprises the steps of, The step of removing the protective layer, the second connecting piece and part of the bit line covering layer to expose the second side wall comprises the following steps: Removing the protective layer through a second etching process; And removing the second connecting piece and part of the bit line covering layer through a third etching process to expose the second side wall.
4. The method for manufacturing the dynamic random access memory according to claim 1, it is characterized in that the method comprises the steps of, The step of removing at least part of the second side wall forming gap and the first sacrificial member forming node groove comprises the following steps: and simultaneously removing at least part of the second side wall and the first sacrificial member through a fourth etching process.
5. The method for manufacturing the dynamic random access memory according to claim 1, it is characterized in that the method comprises the steps of, The protective layer, the bit line cover layer, the first side wall and the peripheral cover layer are formed by the same material.
6. The method for manufacturing the dynamic random access memory according to claim 1, it is characterized in that the method comprises the steps of, The second side wall, the second connecting piece and the first sacrificial piece are made of the same material.
7. A dynamic random access memory, comprising: A substrate provided with an array region and a peripheral region; the active areas are arranged in an array mode and are arranged in the array area; A word line structure disposed in the substrate and passing through the active region; The bit line structure is arranged in the array region and is in contact with the active region, the bit line structure comprises a bit line electrode structure, a bit line side wall and a bit line protection layer, the bit line electrode structure is arranged on the active region, the bit line side wall comprises a first side wall and a second side wall, the first side wall is arranged between the second side wall and the bit line electrode structure, and the bit line protection layer is arranged on the side surface of the bit line side wall; The isolation structure and the node contact plugs are arranged between the bit line structures at intervals, and the node contact plugs are connected with the active area; Landing pads, the landing pads being partially disposed on the node contact plugs and partially disposed on the bit line structures; a storage node disposed on the landing pad; The peripheral region comprises a circuit structure and a peripheral cover layer, and the peripheral cover layer covers the circuit structure; The upper surface of the second side wall below the landing pad is lower than the upper surfaces of the first side wall and the bit line protection layer, and the bit line protection layer is arranged between the upper surface of the second side wall and the landing pad.
8. The dynamic random access memory of claim 7, wherein, An air gap is arranged between the bit line protection layer and the upper surface of the second side wall.
9. The dynamic random access memory of claim 7, wherein, The material of the second side wall comprises silicon oxide, and the material of the bit line protection layer and the material of the first side wall comprise silicon nitride.
10. A dynamic random access memory, characterized in that it is manufactured according to the manufacturing method described in claims 1-6.

Description

Dynamic random access memory and manufacturing method thereof Technical Field The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a dynamic random access memory and a manufacturing method thereof. Background The development of dynamic memories (DRAMs) pursues performance indexes such as high speed, high integration density, low power consumption, etc., and with the miniaturization of semiconductor device structure sizes, product yield is considered under the condition of ensuring critical dimensions, and technical barriers encountered by the existing structures are more and more obvious. Therefore, more novel manufacturing methods are developed on the basis of the existing manufacturing methods, and the method is an advantageous means for breaking the prior art barriers and improving the product yield. Disclosure of Invention According to a first aspect of an embodiment of the present disclosure, there is provided a method for manufacturing a dynamic random access memory, including: The method comprises the steps of providing a substrate, forming an array region and a peripheral region on the substrate, forming an active region in the array region, forming a word line structure in the substrate and penetrating the active region, forming a bit line structure in the array region and contacting the active region, forming a bit line electrode structure on the bit line structure, forming a bit line side wall and a bit line covering layer on the active region, forming a first side wall comprising a first side wall and a second side wall between the second side wall and the bit line electrode structure, forming a bit line covering layer on the side surface and the upper surface of the bit line side wall and the upper surface of the bit line electrode structure, forming an isolation structure in the array region, forming a first sacrificial member and an isolation structure at intervals between the bit line structure, forming a second connecting member in the second sacrificial member on at least part of the bit line structure and on the first sacrificial member on two sides of the bit line structure, forming a peripheral covering layer covering the circuit structure, forming a protective layer on the peripheral covering the circuit structure, covering the peripheral region, removing the protective layer, removing the second connecting member and part of the bit line covering layer, exposing the second side wall, forming a second side wall, removing at least part of the second side wall covering layer, forming a contact pad on the side of the second sacrificial member and the first sacrificial member, forming a contact pad between the first contact pad and the contact pad. In some embodiments, removing the protective layer, the second connection and a portion of the bit line capping layer to expose the second sidewall includes simultaneously removing the protective layer, the second connection and a portion of the bit line capping layer to expose the second sidewall by a first removal process. In some embodiments, removing the protective layer, the second connection and a portion of the bit line capping layer to expose the second sidewall includes removing the protective layer by a second etching process and removing the second connection and a portion of the bit line capping layer by a third etching process to expose the second sidewall. In some embodiments, removing at least a portion of the second sidewall forming void and the first sacrificial member forming node trench includes simultaneously removing at least a portion of the second sidewall and the first sacrificial member by a fourth etching process. In some embodiments, the protective layer, the bit line cap layer, the first sidewall and the peripheral cap layer are formed of the same material. In some embodiments, the second sidewall, the second connector and the first sacrificial member are formed of the same material. According to a second aspect of the disclosed embodiments, a dynamic random access memory is provided, which comprises a substrate, an active region, a word line structure, a bit line structure, a peripheral covering layer and a peripheral covering layer, wherein the substrate is provided with an array region and a peripheral region, the active region is arranged in the array region in an array mode, the word line structure is arranged in the substrate and penetrates through the active region, the bit line structure is arranged in the array region and is in contact with the active region, the bit line structure comprises a bit line electrode structure, a bit line side wall and a bit line protection layer, the bit line electrode structure is arranged on the active region, the bit line side wall comprises a first side wall and a second side wall, the first side wall is arranged between the second side wall and the bit line electrode structure, the bit line protection layer is arranged on the si