CN-122002789-A - Storage array, storage and electronic equipment

Abstract

The application discloses a memory array, a memory and an electronic device, which relate to the technical field of memory, wherein the memory array comprises a plurality of device groups and a first dielectric layer, the first dielectric layer extends along a first direction and is arranged between vertical channels of two vertical field effect transistors in a plurality of device groups, and the vertical channels of the vertical field effect transistors in the same device group are isolated through the first dielectric layer. And, by making the length of the vertical channel in the second direction longer than that in the first direction, a fork plate (forksheet) structure is formed, improving the storage density and overall stability. And by making the length of the vertical channel in the second direction longer than that of the vertical channel in the first direction, the contact area between the vertical channel and the first dielectric layer can be reduced, so that the coupling capacitance between the vertical channels of two vertical field effect transistors in the same device group is reduced.

Inventors

• Huang Hefu
• HU XIANG
• DONG YAOQI
• SU XIN
• XU JUNHAO

Assignees

• 华为技术有限公司

Dates

Publication Date

20260508

Application Date

20241106

Claims (20)

1. 1. A memory array, comprising: A plurality of device groups arranged at intervals along the first direction, each device group including two vertical field effect transistors, each vertical field effect transistor including a vertical channel extending along a third direction, the length of the vertical channel in a second direction being longer than the length thereof in the first direction, the vertical channels of the two vertical field effect transistors in each device group being arranged along the second direction, any two of the third direction, the first direction, and the second direction being perpendicular; and the first dielectric layer extends along the first direction and is arranged between vertical channels of the two vertical field effect transistors in the device groups.
2. 2. The memory array of claim 1, wherein the vertical channel has first and second surfaces opposite in the first direction, and third and fourth surfaces opposite in the second direction, the third surface in contact with the first dielectric layer; Each vertical field effect transistor further includes a gate overlying at least a portion of the first surface, at least a portion of the second surface, and at least a portion of the fourth surface of the vertical channel via a second dielectric layer.
3. 3. The memory array of claim 2, further comprising a plurality of word lines, one of the plurality of word lines being connected to a gate of the vertical field effect transistor disposed on the same side of the first dielectric layer, the gate being part of a word line connected thereto, the first dielectric layer being disposed between the two vertical field effect transistor connected word lines.
4. 4. The memory array of claim 3, wherein the word line comprises a word line barrier layer and a word line metal layer, the word line barrier layer disposed between the word line metal line and the second dielectric layer.
5. 5. The memory array of claim 4, wherein the word line barrier layer covers the first, second, and fourth surfaces of the vertical channel with the second dielectric layer therebetween, and the word line metal layer covers the first, second, and fourth surfaces of the vertical channel with the word line barrier layer and the second dielectric layer therebetween; For two adjacent vertical channels along the first direction, a spacing between the word line metal layers covering opposite portions of the two adjacent vertical channels is greater than or equal to zero.
6. 6. The memory array of claim 3, wherein the word line barrier layer covers the first, second, and fourth surfaces of the vertical channel through the second dielectric layer; for two vertical channels adjacent in the first direction, a spacing between the word line blocking layers covering facing portions of the two adjacent vertical channels is equal to zero.
7. 7. The memory array of any of claims 3-6, wherein the first dielectric layer is in contact with a portion of the word lines or wherein the second dielectric layer is between the first dielectric layer and a portion of the word lines.
8. 8. The memory array of claim 7, wherein a thickness of the second dielectric layer in contact with the first dielectric layer is less than or equal to a thickness of the second dielectric layer in contact with the vertical channel.
9. 9. The memory array of claim 8, wherein the second dielectric layer comprises a first sub-dielectric layer and a second sub-dielectric layer, the first sub-dielectric layer and the second sub-dielectric layer are disposed layer by layer on the first surface, the second surface, and the fourth surface of the vertical channel, and the second sub-dielectric layer is further disposed between the first dielectric layer and the word line.
10. 10. The memory array of any of claims 1-9, wherein the orthographic projection of the vertical channel in the plane of the first direction and the second direction is a first orthographic projection, the orthographic projection of the first dielectric layer in the plane of the first direction and the second direction is a second orthographic projection, and an extension direction of the first orthographic projection is perpendicular to an extension direction of the second projection.
11. 11. The memory array of any of claims 1-10, wherein the vertical field effect transistor further comprises a first electrode and a second electrode disposed on both sides of the vertical channel in the vertical direction, the first dielectric layer further disposed between the first electrodes and between the second electrodes of the two vertical field effect transistors.
12. 12. The memory array of claim 11, wherein the first electrode has first and second surfaces opposite in the first direction and a third surface in the second direction; the third surface of the first electrode is in contact with the first dielectric layer; the second dielectric layer also covers at least a partial region of the first surface and at least a partial region of the second surface of the first electrode.
13. 13. The memory array of claim 12, wherein a thickness of the second dielectric layer in contact with the first electrode is greater than or equal to a thickness of the second dielectric layer in contact with the vertical channel, or The gate also covers the second dielectric layer on the first electrode.
14. 14. The memory array of any of claims 11-13, wherein the second electrode has first and second surfaces opposite in the first direction, and third and fourth surfaces opposite in the second direction; The third surface of the second electrode is in contact with the first dielectric layer, which also covers at least a partial area of the first surface, at least a partial area of the second surface and at least a partial area of the fourth surface of the second electrode.
15. 15. The memory array of claim 14, wherein a thickness of the second dielectric layer in contact with the second electrode is greater than or equal to a thickness of the second dielectric layer in contact with the vertical channel.
16. 16. The memory array of any of claims 1-15, further comprising a trench isolation structure and a plurality of bit lines, the device group disposed on a side of the trench isolation structure, the plurality of bit lines disposed on a side of the vertical field effect transistors facing the trench isolation structure, a first electrode of the vertical field effect transistors aligned along the second direction being connected to one of the plurality of bit lines.
17. 17. The memory array of claim 16, wherein the plurality of bit lines are embedded in the trench isolation structure.
18. 18. The memory array of claim 17, wherein the first dielectric layer is further disposed between the first electrodes of the two vertical field effect transistors, the first dielectric layer further extends into the bit line along the vertical direction, and a height of a portion of the first dielectric layer in the vertical direction is less than a height of the bit line in the vertical direction.
19. 19. A memory comprising a controller and at least one memory array, the controller being electrically connected to the at least one memory array; the at least one memory array is a memory array as claimed in any one of claims 1 to 18.
20. 20. An electronic device comprising a circuit board and the memory of claim 19, wherein the memory is electrically connected to the circuit board.

Description

Storage array, storage and electronic equipment Technical Field The present application relates to the field of memory technologies, and in particular, to a memory array, a memory, and an electronic device. Background In order to continuously increase the memory capacity, the memory cells (cells) of dynamic random access memories (Dynamic RandomAccess Memory, DRAM) are continuously shrinking, for which purpose Vertical field effect transistors (Vertical FieldEffectTransistor, VFET) are present, which can decouple the gate length from the gate pitch, allowing scaling of the transistor density in order to minimize the area occupied by the memory cells (cells). However, since coupling capacitance exists between vertical channels of different vertical field effect transistors, when a gate of a certain vertical field effect transistor is loaded with an on potential, an adjacent vertical field effect transistor is turned on to generate leakage due to the existence of the coupling capacitance, which affects the performance of the DRAM. Disclosure of Invention The embodiment of the application provides a memory array, a memory and an electronic device, which are used for reducing the coupling capacitance between vertical channels of vertical field effect transistors. In a first aspect, an embodiment of the present application provides a memory array, where the memory array includes a plurality of device groups and a first dielectric layer, where the plurality of device groups are disposed at intervals along a first direction, each device group includes two vertical field effect transistors, each vertical field effect transistor includes a vertical channel extending along a third direction, the vertical channels of the two vertical field effect transistors in each device group are arranged along a second direction, and the first dielectric layer extends along the first direction and is disposed between the vertical channels of the two vertical field effect transistors in the plurality of device groups, so that the vertical channels of the vertical field effect transistors in the same device group are isolated by the first dielectric layer, and two vertical field effect transistors in the same device group are disposed on two sides of the first dielectric layer in a back-to-back manner, so as to implement a 4F 2 architecture. And, by making the length of the vertical channel in the second direction longer than that in the first direction, the contact area between the vertical channel and the first dielectric layer can be reduced, thereby reducing the coupling capacitance between the vertical channels of two vertical field effect transistors in the same device group. Wherein any two directions of the third direction, the first direction and the second direction are perpendicular. In one possible embodiment of the application, the vertical channel has a first surface and a second surface opposite in a first direction, and a third surface and a fourth surface opposite in a second direction, the third surface being in contact with the first dielectric layer. And each vertical field effect transistor further comprises a gate electrode covering at least a partial region of the first surface, at least a partial region of the second surface, and at least a partial region of the fourth surface of the vertical channel via the second dielectric layer. Therefore, the vertical channel can be controlled by a tri-gate structure, so that the vertical field effect transistor in the embodiment of the application is formed into the tri-gate transistor, the area of the vertical channel covered by the gate can be further improved, and better current control, higher performance and energy efficiency and lower electric leakage can be realized. In one possible embodiment of the present application, in order to transmit signals to the gates of the vertical field effect transistors, the memory array further includes a plurality of word lines, one of the plurality of word lines is connected to the gates of the vertical field effect transistors disposed on the same side of the first dielectric layer, so as to transmit signals using the word lines as the gates of the vertical field effect transistors. In addition, in order to save the area occupied by the word lines, the grid electrode is arranged to be a part of the word lines connected with the grid electrode, so that the extra manufacturing process and the material cost can be reduced, the higher device integration level can be realized, and the device performance is optimized. In addition, in order to avoid the short circuit of different word lines, a first dielectric layer is arranged between the word lines connected with two vertical field effect transistors in the same device group, so that the two word lines are isolated through the first dielectric layer, and the reliability is improved. In one possible embodiment of the present application, to improve the adhesion of the metal, the wor