CN-122002790-A - Storage structure, preparation method thereof and electronic equipment

Abstract

The application relates to a memory structure and a preparation method thereof, wherein the memory structure comprises a word line structure, a bit line, a semiconductor layer and a capacitor structure. The word line structure includes a first word line and a second word line disposed opposite to each other in a first direction. The first word line and the second word line extend along the second direction. The bit line extends along a first direction and penetrates through the first word line and the second word line. The semiconductor layer is located between the first word line and the second word line and is arranged around the bit line. The capacitor structure comprises a first electrode, a capacitor dielectric layer and a second electrode which are sequentially arranged around the semiconductor layer. The second electrode has a groove on a side facing the bit line, the groove being recessed in a direction away from the bit line. The first electrode includes a first portion and a second portion connected to each other. The first portion is located in the groove and the second portion is located outside the groove. And the orthographic projection of the second electrode on the bit line overlaps with the orthographic projection of the second portion on the bit line. The application can effectively improve the performance of the storage structure.

Inventors

• ZHI CHENGBO
• SHAO FENG
• AI XUEZHENG
• YU YONG
• KANG BOWEN

Assignees

• 北京超弦存储器研究院

Dates

Publication Date

20260508

Application Date

20241107

Claims (17)

1. 1. A memory structure, comprising: a word line structure including a first word line and a second word line which are parallel and are oppositely arranged in a first direction, wherein the first word line and the second word line extend along a second direction, and the first direction is intersected with the second direction; A bit line extending in a first direction and penetrating the first word line and the second word line; a semiconductor layer located between the first word line and the second word line and disposed around the bit line; The capacitor structure comprises a first electrode, a capacitor dielectric layer and a second electrode, wherein the first electrode, the capacitor dielectric layer and the second electrode are sequentially arranged around the semiconductor layer, a groove is formed in one side, facing the bit line, of the second electrode, the groove is recessed along the direction away from the bit line, the first electrode comprises a first part and a second part which are mutually connected, the first part is positioned in the groove, the second part is positioned outside the groove, the orthographic projection of the second electrode on the bit line overlaps with the orthographic projection of the second part on the bit line, and the capacitor dielectric layer is positioned between the first electrode and the second electrode.
2. 2. The method of manufacturing a memory structure of claim 1, wherein a width of the second portion in the first direction is greater than a width of the first portion in the first direction.
3. 3. The storage structure of claim 1, wherein the storage structure further comprises: an insulating dielectric layer comprising a first dielectric portion and a second dielectric portion connected to each other, the first dielectric portion being located on the bit line sidewall, the second dielectric portion being located between the semiconductor layer and the word line structure; the capacitance medium layer extends from the inner groove wall of the groove to the surface of the second medium part far away from the word line structure through the end face of the second electrode facing the bit line.
4. 4. A memory structure according to claim 3, wherein the second portion comprises a first sub-portion and a second sub-portion connected to each other, the first sub-portion being located on the surface of the capacitor dielectric layer on both sides in the first direction, and the second sub-portion being located on the surface of the insulating dielectric layer on both sides in the first direction.
5. 5. A memory structure according to claim 3, wherein the second dielectric portion is further adapted to cover a surface of the second electrode remote from the capacitive dielectric layer.
6. 6. The storage structure of claim 5, wherein, The insulating medium layer is provided with at least one opening in the third direction, the opening exposes the second electrode, the third direction intersects with the second direction, and the third direction intersects with the first direction; The memory structure further comprises at least one third electrode located on at least one side of the capacitive structure in the third direction and connected to the second electrode through the opening.
7. 7. The memory structure according to claim 1, wherein the first word line and/or the second word line includes a gate portion surrounding the bit line and a connection portion connecting the gate portion in the second direction, and the gate portion protrudes from the connection portion to a third direction intersecting the second direction and intersecting the first direction to cover the semiconductor layer in the same first word line or second word line.
8. 8. The storage structure of claim 1, further comprising a substrate, wherein the second direction is parallel to the substrate, and wherein the first direction is perpendicular to the substrate.
9. 9. A method of manufacturing a memory structure, comprising: Providing a substrate, and forming a stacked layer on the substrate, wherein the stacked layer comprises a first material layer and a second material layer which are alternately stacked, the second material layer comprises a first sub-layer, a second sub-layer and a third sub-layer which are sequentially arranged along a first direction, and the first direction is perpendicular to the substrate; Forming a device hole in the stacked layer, wherein the device hole comprises a bit line hole and a lateral hole which are communicated with each other, the bit line hole penetrates through the stacked layer along a first direction, and the lateral hole is positioned in the second sub-layer and surrounds the bit line hole; Forming a capacitor structure in the lateral hole, wherein the capacitor structure partially fills the lateral hole and comprises a first electrode, a capacitor dielectric layer and a second electrode which are sequentially arranged from inside to outside, the second electrode covers the bottom of the lateral hole and part of the side wall to form a groove facing one side of the bit line hole, the capacitor dielectric layer covers the second electrode, the first electrode is positioned on the surface of the capacitor dielectric layer far away from the second electrode and comprises a first part and a second part which are mutually connected, the first part is positioned in the groove, the second part is positioned outside the groove, and the orthographic projection of the second electrode on the bit line hole wall overlaps with the orthographic projection of the second part on the bit line hole wall; Forming a semiconductor layer on the first electrode, the semiconductor layer filling the remaining space of the lateral hole; Forming a bit line in the bit line hole; Based on the first sub-layer and the third sub-layer, a first word line and a second word line are formed, the first word line and the second word line being parallel and extending in a second direction, the second direction being parallel to the substrate.
10. 10. The method of manufacturing a memory structure of claim 9, wherein a width of the second portion in the first direction is greater than a width of the first portion in the first direction.
11. 11. The method of manufacturing a memory structure of claim 9, wherein prior to forming a capacitor structure in the lateral via, comprising: Forming an insulating medium material layer on the hole wall of the device hole and the upper surface of the stacking layer; after the bit line is formed in the bit line hole, the method comprises the following steps: and removing the insulating dielectric material layer on the upper surface of the stacked layers to form an insulating dielectric layer.
12. 12. The method of claim 11, wherein forming a capacitor structure in the lateral via comprises: Forming the second electrode on the surface of the insulating dielectric material layer positioned in the lateral hole; Forming a capacitance dielectric material layer on the surface of the second electrode and the surface of the insulating dielectric material layer; forming a first conductive material layer on the surface of the capacitance dielectric material layer, wherein the first conductive material layer fills the residual space of the device hole; and carrying out back etching on the first conductive material layer and the capacitance medium material layer to form the first electrode and the capacitance medium layer.
13. 13. The method of manufacturing a memory structure according to claim 12, wherein the second portion includes a first sub-portion and a second sub-portion that are connected to each other, and the etching back the first conductive material layer and the capacitor dielectric material layer to form the first electrode and the capacitor dielectric layer includes: Back etching the first conductive material layer and the capacitance dielectric material layer to form the capacitance dielectric layer, the first part and the first sub-part; and forming a second sub-part covering the capacitor dielectric layer and the first sub-part.
14. 14. The method of claim 9, wherein forming device holes in the stacked layers comprises: forming a dummy bit line through the stacked layers; forming a plurality of first isolation structures arranged at intervals through the stacked layer, wherein the first isolation structures extend along the second direction and are arranged along a third direction, the stacked layer between the adjacent first isolation structures comprises a first stacked part and a second stacked part, the first stacked part surrounds the dummy bit line, the second stacked part is connected with the first stacked part in the second direction, the first stacked part protrudes from the second stacked part to the third direction so as to define a device hole area, the third direction is parallel to the substrate, and the third direction is intersected with the second direction; Removing the dummy bit line to form the bit line hole; and etching the second sub-layer laterally from the bit line hole to form the lateral hole.
15. 15. The method of manufacturing a memory structure according to claim 14, wherein forming a first word line and a second word line based on the first sub-layer and the third sub-layer comprises: Removing the first isolation structure to form an isolation groove; Laterally etching the first sub-layer and the third sub-layer from the isolation groove to form a first space and a second space; and filling conductive materials in the first space and the second space to form the first word line and the second word line.
16. 16. The method of manufacturing a memory structure according to claim 15, wherein the filling the first space and the second space with a conductive material after forming the first word line and the second word line further comprises: Backfilling the isolation groove to form a second isolation structure; forming an electrode groove extending along the second direction in the second isolation structure, wherein the electrode groove exposes the second electrode in the third direction; And a third electrode is formed in the electrode groove and is connected with the second electrode.
17. 17. An electronic device comprising a storage structure according to any one of claims 1 to 8 or a storage structure prepared by a method according to any one of claims 9 to 16.

Description

Storage structure, preparation method thereof and electronic equipment Technical Field The present application relates to the field of integrated circuits, and in particular, to a memory structure, a method for manufacturing the same, and an electronic device. Background With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing, so that any minor differences in process production may affect the performance of the devices. In order to reduce the cost of the product as much as possible, it is desirable to make as many device cells as possible on a limited substrate. Since moore's law emerged, various semiconductor device designs and process optimizations have been proposed in the industry to meet the needs of current products. Disclosure of Invention Based on the above, the application provides a storage structure and a preparation method thereof. A storage structure, comprising: a word line structure including a first word line and a second word line which are parallel and are oppositely arranged in a first direction, wherein the first word line and the second word line extend along a second direction, and the first direction is intersected with the second direction; A bit line extending in a first direction and penetrating the first word line and the second word line; a semiconductor layer located between the first word line and the second word line and disposed around the bit line; The capacitor structure comprises a first electrode, a capacitor dielectric layer and a second electrode, wherein the first electrode, the capacitor dielectric layer and the second electrode are sequentially arranged around the semiconductor layer, a groove is formed in one side, facing the bit line, of the second electrode, the groove is recessed along the direction away from the bit line, the first electrode comprises a first part and a second part which are mutually connected, the first part is positioned in the groove, the second part is positioned outside the groove, the orthographic projection of the second electrode on the bit line overlaps with the orthographic projection of the second part on the bit line, and the capacitor dielectric layer is positioned between the first electrode and the second electrode. In one embodiment, the width of the second portion in the first direction is greater than the width of the first portion in the first direction. In one embodiment, the storage structure further comprises: an insulating dielectric layer comprising a first dielectric portion and a second dielectric portion connected to each other, the first dielectric portion being located on the bit line sidewall, the second dielectric portion being located between the semiconductor layer and the word line structure; the capacitance medium layer extends from the inner groove wall of the groove to the surface of the second medium part far away from the word line structure through the end face of the second electrode facing the bit line. In one embodiment, the second portion includes a first sub-portion and a second sub-portion that are connected to each other, where the first sub-portion is located on the surface of the capacitor dielectric layer on two sides in the first direction, and the second sub-portion is located on the surface of the insulating dielectric layer on two sides in the first direction. In one embodiment, the second dielectric portion may further cover a surface of the second electrode away from the capacitive dielectric layer. In one of the embodiments of the present invention, The insulating medium layer is provided with at least one opening in the third direction, the opening exposes the second electrode, the third direction intersects with the second direction, and the third direction intersects with the first direction; The memory structure further comprises at least one third electrode located on at least one side of the capacitive structure in the third direction and connected to the second electrode through the opening. In one embodiment, the first word line and/or the second word line includes a gate portion surrounding the bit line and a connection portion connecting the gate portion in the second direction, the gate portion protruding from the connection portion to a third direction to cover the semiconductor layer, the third direction intersecting the second direction and the third direction intersecting the first direction, in the same first word line or second word line. In one embodiment, the memory structure further comprises a substrate, the second direction is parallel to the substrate, and the first direction is perpendicular to the substrate. A method of fabricating a memory structure, comprising: Providing a substrate, and forming a stacked layer on the substrate, wherein the stacked layer comprises a first material layer and a second material layer which are alternately s