CN-122002791-A - Semiconductor structure, manufacturing method thereof and electronic equipment

Abstract

A semiconductor structure, a method of manufacturing the same, and an electronic device. The semiconductor structure comprises an active column extending along a vertical direction, a word line extending along a first horizontal direction and coupled with the active column to form a transistor, and a bit line extending along a second horizontal direction and coupled with the active column, wherein the second horizontal direction intersects the first horizontal direction, the word line comprises a first conductive pattern and a second conductive pattern, the first conductive pattern is provided with first openings and second openings which are alternately arranged along the first horizontal direction, the active column is located in the first openings, the second conductive pattern is located in the second openings, and the resistivity of the second conductive pattern is smaller than that of the first conductive pattern. The semiconductor structure is beneficial to reducing the resistance of word lines and improving the performance of devices.

Inventors

• XUE XINGKUN
• LIU JINYING
• MA DI
• QIU YUNSONG

Assignees

• 长鑫科技集团股份有限公司

Dates

Publication Date

20260508

Application Date

20241108

Claims (10)

1. 1. A semiconductor structure, comprising: an active column extending in a vertical direction; a word line extending in a first horizontal direction and coupled with the active pillar to form a transistor; A bit line extending along a second horizontal direction and coupled with the active pillar, wherein the second horizontal direction intersects the first horizontal direction; The word line comprises a first conductive pattern and a second conductive pattern which are connected with each other, the first conductive pattern is provided with first holes and second holes which are alternately arranged along the first horizontal direction, the active pillars are positioned in the first holes, the second conductive pattern is positioned in the second holes, and the resistivity of the second conductive pattern is smaller than that of the first conductive pattern.
2. 2. The semiconductor structure of claim 1, wherein the first hole is surrounded by a first extension and a second extension of the first conductive pattern, the first extension extending in the first horizontal direction, the second extension extending in the second horizontal direction, the second extension having a width greater than 1/2 of a width of the first extension.
3. 3. The semiconductor structure of claim 2, wherein a width of the second extension is less than a width of the first extension.
4. 4. A semiconductor structure according to claim 2 or 3, wherein the second hole is surrounded by a third extension of the first conductive pattern extending in the first horizontal direction and the second extension, the third extension having a width equal to the width of the second extension.
5. 5. A semiconductor structure according to any of claims 1-3, wherein the first hole is a via and the second hole is a via.
6. 6. A semiconductor structure according to any of claims 1-3, wherein the first hole is a via and the second hole is a blind hole.
7. 7. A semiconductor structure according to any of claims 1-3, wherein the material of the first conductive pattern comprises titanium nitride or tantalum nitride and the material of the second conductive pattern comprises molybdenum or tungsten.
8. 8. The semiconductor structure of any of claims 1-3, further comprising: And a data storage element coupled to the transistor.
9. 9. A method of fabricating a semiconductor structure, comprising: Providing a semiconductor substrate; etching the semiconductor substrate to form an active column extending in a vertical direction; Forming a word line, wherein the word line extends along a first horizontal direction and is coupled with the active pillar; Forming a bit line, wherein the bit line extends along a second horizontal direction and is coupled with the active pillar, and the second horizontal direction intersects the first horizontal direction; the word line comprises a first conductive pattern and a second conductive pattern, the first conductive pattern is provided with first holes and second holes which are alternately arranged along the first horizontal direction, the active pillars are located in the first holes, the second conductive pattern is located in the second holes, and the resistivity of the second conductive pattern is smaller than that of the first conductive pattern.
10. 10. An electronic device, comprising: processor, and A memory, wherein the memory is coupled to the processor, the memory comprising the semiconductor structure of any of claims 1-8.

Description

Semiconductor structure, manufacturing method thereof and electronic equipment Technical Field The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure, a manufacturing method thereof and electronic equipment. Background The dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory. Compared with a static memory, the DRAM has the advantages of simpler structure, lower manufacturing cost and higher storage density, and along with the development of technology, the DRAM is increasingly widely applied. A Dynamic Random Access Memory (DRAM) includes a plurality of memory cells, each memory cell including a transistor and a capacitor coupled to the transistor. One of the source and drain of the transistor is connected to the bit line, the other of the source and drain of the transistor is connected to the capacitor, and the gate of the transistor is connected to the word line. Under control of the word line, the transistor writes data information to or reads data information from the capacitor through the bit line. With the development of semiconductor technology, an architecture scheme has been proposed in which a planar transistor or a buried transistor in a DRAM is changed to a vertical transistor (the channel of which extends at least partially in a vertical direction). In this architecture, vertically extending active pillars are formed on a substrate, and gates are formed on sidewalls of the active pillars. Disclosure of Invention According to a first aspect of an embodiment of the present disclosure, there is provided a semiconductor structure including an active pillar extending in a vertical direction, a word line extending in a first horizontal direction and coupled with the active pillar to form a transistor, a bit line extending in a second horizontal direction and coupled with the active pillar, wherein the second horizontal direction intersects the first horizontal direction, wherein the word line includes first conductive patterns and second conductive patterns connected to each other, the first conductive patterns having first holes and second holes alternately arranged in the first horizontal direction, the active pillar being located in the first holes, the second conductive patterns being located in the second holes, and the second conductive patterns having a resistivity smaller than that of the first conductive patterns. In some embodiments, the first hole is surrounded by a first extension and a second extension of the first conductive pattern, the first extension extending in the first horizontal direction, the second extension extending in the second horizontal direction, the second extension having a width greater than 1/2 of the width of the first extension. In some embodiments, the width of the second extension is less than the width of the first extension. In some embodiments, the second hole is surrounded by a third extension of the first conductive pattern and the second extension, the third extension extending along the first horizontal direction, a width of the third extension being equal to a width of the second extension. In some embodiments, the first hole is a through hole and the second hole is a through hole. In some embodiments, the first hole is a through hole and the second hole is a blind hole. In some embodiments, the material of the first conductive pattern comprises titanium nitride and the material of the second conductive pattern comprises molybdenum or tungsten. In some embodiments, the semiconductor structure further includes a data storage element coupled to the transistor. According to a second aspect of embodiments of the present disclosure, there is provided a method of manufacturing a semiconductor structure, including providing a semiconductor substrate, etching the semiconductor substrate to form an active pillar extending in a vertical direction, forming a word line, wherein the word line extends in a first horizontal direction and is coupled with the active pillar, forming a bit line, wherein the bit line extends in a second horizontal direction and is coupled with the active pillar, the second horizontal direction intersecting the first horizontal direction, wherein the word line includes a first conductive pattern having first holes and second holes alternately arranged in the first horizontal direction, and a second conductive pattern in the second holes, the second conductive pattern having a resistivity smaller than that of the first conductive pattern. According to a third aspect of embodiments of the present disclosure, there is provided an electronic device comprising a processor and a memory provided by any of the embodiments of the present disclosure. The memory is coupled to the processor. In the semiconductor structure provided by the embodiment of the disclosure, the word line is composed of the first conductive pattern with relatively high