CN-122002792-A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Abstract

The application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, a channel layer positioned on the substrate extending along a first direction perpendicular to a top surface of the substrate and including an inverted trapezoidal cross-sectional profile, and a word line including a word line dielectric layer and a word line conductive layer uniformly and laterally surrounding the channel layer, the word line conductive layer laterally and partially surrounding the word line dielectric layer, extending along a second direction parallel to a top surface of the substrate and including an inverted trapezoidal cross-sectional profile.

Inventors

• LV ZENGFU

Assignees

• 南亚科技股份有限公司

Dates

Publication Date

20260508

Application Date

20250411

Priority Date

20241106

Claims (20)

1. 1. A semiconductor device, comprising: A substrate; A channel layer positioned above the substrate, extending in a first direction perpendicular to a top surface of the substrate and including an inverted trapezoidal cross-sectional profile, and A word line, comprising: A word line dielectric layer closely and laterally surrounding the channel layer, and A word line conductive layer laterally and partially surrounding the word line dielectric layer, extending along a second direction parallel to a top surface of the substrate, and comprising an inverted trapezoidal cross-sectional profile.
2. 2. The semiconductor device of claim 1, further comprising a bit line positioned below and electrically coupled to said channel layer.
3. 3. The semiconductor device of claim 2, further comprising a bit line contact positioned between said channel layer and said bit line.
4. 4. The semiconductor device of claim 3, wherein said bit line is positioned in said substrate and extends along a third direction perpendicular to said second direction.
5. 5. The semiconductor device of claim 3, wherein said bit line is positioned on said substrate and extends along a third direction perpendicular to said second direction.
6. 6. The semiconductor device of claim 3, further comprising a storage node structure positioned on and electrically connected to said channel layer.
7. 7. The semiconductor device of claim 6, wherein said storage node structure comprises: A first electrode layer positioned on the channel layer and electrically connected to the channel layer; a second electrode layer positioned on the first electrode layer, and An intermediate insulating layer is positioned between the first electrode layer and the second electrode layer to electrically isolate the first electrode layer from the second electrode layer.
8. 8. The semiconductor device of claim 1, further comprising a bit line positioned on and electrically coupled to said channel layer.
9. 9. The semiconductor device of claim 8, further comprising a bit line contact positioned between said bit line and said channel layer.
10. 10. The semiconductor device of claim 9, further comprising a storage node structure positioned below and electrically connected to said channel layer.
11. 11. The semiconductor device of claim 1, wherein the channel layer comprises doped polysilicon, doped poly-germanium, or doped poly-silicon-germanium.
12. 12. The semiconductor device of claim 1, wherein the wordline dielectric layer comprises a high dielectric constant dielectric material, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.
13. 13. The semiconductor device of claim 1, wherein the word line conductive layer comprises tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide, metal nitride, transition metal aluminide, or a combination thereof.
14. 14. A semiconductor device, comprising: A substrate; A channel layer positioned above the substrate and extending in a first direction perpendicular to a top surface of the substrate, wherein a width of the top surface of the channel layer is greater than a width of a bottom surface of the channel layer, and A word line, comprising: A word line dielectric layer closely and laterally surrounding the channel layer, and A word line conductive layer laterally and partially surrounding the word line dielectric layer and extending in a second direction parallel to the top surface of the substrate, wherein a width of a top surface of the word line conductive layer is greater than a width of a bottom surface of the word line conductive layer.
15. 15. The semiconductor device of claim 14, further comprising a bit line positioned below and electrically coupled to said channel layer.
16. 16. The semiconductor device of claim 15, further comprising a bit line contact positioned between said channel layer and said bit line.
17. 17. The semiconductor device of claim 16, wherein said bit line is positioned in said substrate and extends along a third direction perpendicular to said second direction.
18. 18. The semiconductor device of claim 16, wherein said bit line is positioned on said substrate and extends along a third direction perpendicular to said second direction.
19. 19. The semiconductor device of claim 16, further comprising a storage node structure positioned on and electrically connected to said channel layer.
20. 20. The semiconductor device of claim 19, wherein the storage node structure comprises: A first electrode layer positioned on the channel layer and electrically connected to the channel layer; a second electrode layer positioned on the first electrode layer, and An intermediate insulating layer is positioned between the first electrode layer and the second electrode layer to electrically insulate the first electrode layer from the second electrode layer.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips Technical Field The present application claims priority to U.S. patent application Ser. No. 18/938,457 (i.e., priority date "day 11, month 6 of 2024"), the contents of which are incorporated herein by reference in their entirety. The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device having a vertical channel layer and a method of manufacturing a semiconductor device having a vertical channel layer. Background Semiconductor devices are used in a variety of electronic applications such as personal computers, cellular phones, digital cameras, and other electronic equipment. Semiconductor devices are continually shrinking in size to meet the increasing demands for computing power. However, various problems occur in the shrinking process, and these problems are increasing. Thus, challenges remain in terms of improving quality, yield, performance, and reliability, and reducing complexity. The above description of "prior art" merely provides background, and it is not admitted that the above description of "prior art" reveals the subject matter of the present disclosure, does not constitute prior art to the present disclosure, and any description of "prior art" above should not be taken as part of any of the present disclosure. Disclosure of Invention An embodiment of the present disclosure provides a semiconductor device including a substrate, a channel layer positioned above the substrate, extending along a first direction perpendicular to a top surface of the substrate, and including an inverted trapezoidal cross-sectional profile, and a word line including a word line dielectric layer immediately and laterally surrounding the channel layer, and a word line conductive layer laterally and partially surrounding the word line dielectric layer, extending along a second direction parallel to a top surface of the substrate, and including an inverted trapezoidal cross-sectional profile. Another embodiment of the present disclosure provides a semiconductor device including a substrate, a channel layer positioned over the substrate and extending along a first direction perpendicular to a top surface of the substrate, wherein a width of a top surface of the channel layer is greater than a width of a bottom surface of the channel layer, and a word line including a word line dielectric layer that snugly and laterally surrounds the channel layer, and a word line conductive layer that laterally and partially surrounds the word line dielectric layer and extends along a second direction parallel to a top surface of the substrate, wherein a width of a top surface of the word line conductive layer is greater than a width of a bottom surface of the word line conductive layer. Another embodiment of the present disclosure provides a method of manufacturing a semiconductor device, comprising providing a substrate, forming a lower dielectric layer over the substrate, forming an intermediate dielectric layer over the lower dielectric layer, forming a word line trench penetrating the intermediate dielectric layer, exposing the lower dielectric layer and comprising an inverted trapezoidal cross-sectional profile, forming a word line conductive layer filling the word line trench, forming an upper dielectric layer over the intermediate dielectric layer, forming a via opening penetrating the upper dielectric layer, the word line conductive layer and the lower dielectric layer to expose the substrate, and forming a word line dielectric layer on a sidewall of the via opening in a close proximity, and forming a via layer filling the via opening. The word line conductive layer and the word line dielectric layer together are configured as a word line. Due to the design of the semiconductor device of the present disclosure, the process window for forming the channel layer can be increased by employing the word line conductive layer and the channel layer having the inverted trapezoidal cross-sectional profile. Accordingly, defects in manufacturing the semiconductor device can be reduced, and yield in manufacturing the semiconductor device can be improved. The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Other technical features and advantages that form the subject of the claims of the present disclosure are described below. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the disclosu