CN-122002793-A - Semiconductor device with stepped word line dielectric material and method of fabricating the same

Abstract

The application discloses a semiconductor element and a manufacturing method of the semiconductor element. The semiconductor device includes a channel layer including a channel extending along a first direction and including a first region and a second region arranged sequentially along the first direction, a source extending from the second region along the first direction, and a drain extending from the first region along a direction opposite to the first direction, and a word line structure including an inner word line dielectric layer surrounding the first region of the channel, an outer word line dielectric layer surrounding the second region of the channel and the inner word line dielectric layer, and a word line conductive layer surrounding the outer word line dielectric layer.

Inventors

• CAI ZHENYU

Assignees

• 南亚科技股份有限公司

Dates

Publication Date

20260508

Application Date

20250425

Priority Date

20241108

Claims (19)

1. 1. A semiconductor element, comprising: a channel layer, comprising: A channel extending along a first direction and including a first region and a second region arranged in sequence along the first direction; A source extending from the second region along the first direction, and A drain extending from the first region along a direction opposite to the first direction, and A wordline structure comprising: an inner word line dielectric layer surrounding the first region of the channel; An outer word line dielectric layer surrounding the second region of the channel and the inner word line dielectric layer, and A word line conductive layer surrounding the outer word line dielectric layer.
2. 2. The semiconductor device of claim 1, further comprising a storage node structure contacting said drain.
3. 3. The semiconductor device of claim 2, wherein the storage node structure comprises: A first electrode contacting the drain electrode; a second electrode adjacent to the first electrode, and And a node dielectric layer between the first electrode and the second electrode for electrically isolating the first electrode and the second electrode.
4. 4. The semiconductor device of claim 2, further comprising a bit line contacting said source.
5. 5. The semiconductor device of claim 4, wherein said word line structure extends along a second direction perpendicular to said first direction.
6. 6. The semiconductor device of claim 5, wherein said bit line extends along a third direction perpendicular to said first direction and said second direction.
7. 7. The semiconductor device of claim 6, further comprising a top dielectric layer over said storage node structure, said source and said drain.
8. 8. The semiconductor device of claim 7, further comprising a wordline cover layer on said top dielectric layer and covering said wordline structure.
9. 9. The semiconductor device of claim 8, further comprising a node cap layer between said storage node structure and said word line cap layer.
10. 10. The semiconductor device of claim 9, further comprising a channel fill dielectric layer between said storage node structure and said word line structure.
11. 11. The semiconductor device of claim 10, wherein a top surface of said wordline cladding layer is substantially coplanar with a top surface of said bitline.
12. 12. The semiconductor device of claim 10, wherein a top surface of said node cap layer is substantially coplanar with a top surface of said channel fill dielectric layer.
13. 13. The semiconductor device of claim 10, wherein a top surface of said node cap layer is substantially coplanar with a top surface of said word line conductive layer.
14. 14. The semiconductor device of claim 10, wherein a ratio of a dimension of said first region to a dimension of a sum of said first region and said second region is between about 0.15 and about 0.85.
15. 15. The semiconductor device of claim 10, wherein a thickness of said inner word line dielectric layer is substantially the same as a thickness of said outer word line dielectric layer.
16. 16. The semiconductor device of claim 10, wherein a thickness of said inner word line dielectric layer is different from a thickness of said outer word line dielectric layer.
17. 17. The semiconductor device of claim 10, wherein said inner word line dielectric layer and said outer word line dielectric layer comprise the same material.
18. 18. The semiconductor device of claim 10, wherein said inner word line dielectric layer and said outer word line dielectric layer comprise different materials.
19. 19. The semiconductor device of claim 10, wherein a ratio of a thickness of said outer word line dielectric layer to a thickness of a stack of said inner word line dielectric layer and said outer word line dielectric layer is between about 0.16 and about 0.50.

Description

Semiconductor device with stepped word line dielectric material and method of fabricating the same Technical Field The priority of U.S. patent application Ser. No. 18/941,085 (i.e., priority date "day 11/8 of 2024"), the contents of which are incorporated herein by reference in their entirety, is claimed. The present disclosure relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device with a stepped word line dielectric material and a method of fabricating the same. Background Semiconductor devices are used in a variety of electronic applications such as personal computers, cell phones, digital cameras, and other electronic devices. The size of semiconductor devices is continually shrinking to meet the increasing demands for computing power. However, many problems also occur during downsizing, and these problems are also increasing continuously. Thus, challenges remain in improving quality, yield, performance, and reliability, and reducing complexity. The discussion of the prior art paragraphs merely provides background information. Statements in the discussion of the prior art paragraphs do not constitute an admission that the disclosure in this paragraph constitutes prior art with respect to the present disclosure and any part of the discussion of the prior art paragraphs is not used as an admission that any part of the present disclosure, including the part of the discussion of the prior art paragraphs, constitutes prior art with respect to the present disclosure. Disclosure of Invention One aspect of the present disclosure provides a semiconductor device including a channel layer including a channel extending along a first direction and including a first region and a second region arranged sequentially along the first direction, a source extending from the second region along the first direction, and a drain extending from the first region along an opposite direction of the first direction, and a word line structure including an inner word line dielectric layer surrounding the first region of the channel, an outer word line dielectric layer surrounding the second region of the channel and the inner word line dielectric layer, and a word line conductive layer surrounding the outer word line dielectric layer. Another aspect of the present disclosure provides a semiconductor device including a support substrate, a plurality of channel layers disposed on a top surface of the support substrate, parallel to each other, extending in a first direction parallel to the top surface of the support substrate, and including a plurality of channels including a first region and a second region, respectively, arranged in sequence along the first direction, a plurality of sources extending from the second region along the first direction, a plurality of drains extending from the first region along a direction opposite to the first direction, respectively, and a word line structure extending along a second direction perpendicular to the first direction and parallel to the top surface of the support substrate, and including an inner word line dielectric layer surrounding the plurality of first regions, an outer word line dielectric layer surrounding the plurality of second regions and the inner word line dielectric layer, and a word line conductive layer surrounding the outer word line dielectric layer, and a plurality of bit lines extending in a direction perpendicular to the top surface of the support substrate. Another aspect of the present disclosure is to provide a method of manufacturing a semiconductor device, comprising providing a support substrate sequentially including a storage node region, a channel region, and a bit line region along a first direction, wherein the channel region sequentially includes a first source/drain region, a word line region including a first region and a second region, and a second source/drain region along the first direction, sequentially stacking a bottom stop layer, a sacrificial layer, and a top dielectric layer on the support substrate, forming a channel layer at the channel region by selectively removing the sacrificial layer in the channel region, wherein the channel layer includes a channel in the word line region, a drain in the first source/drain region, and a source in the second source/drain region, and forming a word line structure including an inner word line dielectric layer covering the first region of the channel, an outer word line dielectric layer covering the inner word line dielectric layer and the first word line dielectric layer of the channel, and an outer word line dielectric layer covering the outer word line dielectric layer of the second channel. Due to the design of the semiconductor device of the present invention, the gate induced drain leakage current can be reduced by employing a thicker word line dielectric layer composed of the inner word line dielectric layer 171 and the outer word line