CN-122002796-A - Memory device including gate capping layer

Abstract

According to an embodiment of the present disclosure, a memory device may include a substrate including an active region, a word line embedded in the substrate and crossing the active region, a gate insulating layer surrounding side surfaces and a lower surface of the word line, a gate capping layer disposed on an inner side surface of the gate insulating layer on the word line, and a bit line contact contacting the active region disposed between the word lines and having a side surface facing the gate capping layer and recessed toward a center of the bit line contact.

Inventors

• JIN XINGSHOU
• Yuan Nashi
• JIN SHENGJI

Assignees

• 爱思开海力士有限公司

Dates

Publication Date

20260508

Application Date

20250725

Priority Date

20241104

Claims (19)

1. 1. A memory device, comprising: A substrate comprising an active region; a word line embedded in the substrate, the word line intersecting the active region; a gate insulating layer surrounding side surfaces and a lower surface of the word line; A gate cover layer disposed on an inner side surface of the gate insulating layer, and A bit line contact in contact with the active region disposed between word lines, the bit line contact having a side surface facing the gate cap layer and recessed toward a center of the bit line contact.
2. 2. The memory device of claim 1, further comprising: a buffer layer disposed on the gate capping layer, Wherein the buffer layer is in contact with an upper surface of the word line.
3. 3. The memory device of claim 1, wherein the gate cap layer covers an entire upper surface of the word line.
4. 4. The memory device of claim 3, further comprising: a buffer layer disposed on the gate capping layer, Wherein a lowermost surface of the buffer layer is in contact with the gate capping layer in a region between inner side surfaces of the gate capping layer.
5. 5. The memory device of claim 4, further comprising: A spacer surrounding the side surface of the bit line contact, Wherein an outer side surface of the spacer is in contact with the buffer layer and the gate capping layer.
6. 6. The memory device of claim 5, wherein the lowermost surface of the buffer layer is at a lower level than a lower surface of the bit line contact.
7. 7. The memory device of claim 1, wherein, The bit line contact includes a first section and a second section located on and continuous with the first section, and An angle between a side surface of the first section and an upper surface of the substrate is different from an angle between a side surface of the second section and the upper surface of the substrate.
8. 8. The memory device of claim 1, wherein, The bit line contact includes a first section and a second section located on and continuous with the first section, and Wherein the area of the upper surface of the first section is smaller than the area of the lower surface of the second section.
9. 9. The memory device of claim 2, wherein the gate cap layer comprises a nitride and the buffer layer comprises an oxide.
10. 10. A memory device, comprising: A substrate comprising an active region; A word line embedded in the substrate and intersecting the active region; a gate insulating layer surrounding side surfaces and a lower surface of the word line; a gate capping layer disposed on an inner side surface of the gate insulating layer on the word line; A buffer layer disposed on the gate cap layer, and A bit line contact comprising a first section in contact with the active region between a word line and a second section on and continuous with the first section, wherein an angle formed by a side surface of the first section and an upper surface of the substrate is different from an angle formed by a side surface of the second section and the upper surface of the substrate.
11. 11. The memory device of claim 10, wherein a side surface of the bit line contact is recessed toward a center of the bit line contact.
12. 12. The memory device of claim 11, wherein the buffer layer is in contact with an upper surface of the word line.
13. 13. The memory device of claim 11, wherein the buffer layer fills a space between inside surfaces of the gate capping layer.
14. 14. The memory device of claim 11, wherein the gate cap layer covers an entire upper surface of the word line.
15. 15. The memory device of claim 11, wherein an angle between the side surface of the first section and the upper surface of the substrate is greater than an angle between the side surface of the second section and the upper surface of the substrate.
16. 16. The memory device of claim 11, wherein an area of an upper surface of the first section is smaller than an area of a lower surface of the second section.
17. 17. A memory device, comprising: A substrate comprising an active region; A bit line contact in contact with the active region, having a side surface recessed toward a center of the bit line contact, and including a first section and a second section, the second section being located on and continuous with the first section; A gate cap layer on a side surface of the first section of the bit line contact, and A buffer layer is located on a side surface of the second section of the bit line contact.
18. 18. The memory device of claim 17, further comprising: a word line embedded in the substrate and intersecting the active region, and A gate insulating layer surrounding side surfaces and a lower surface of the word line, Wherein the gate capping layer is disposed on an inner side surface of the gate insulating layer.
19. 19. The memory device of claim 17, wherein the buffer layer fills a space between inside surfaces of the gate capping layer.

Description

Memory device including gate capping layer Cross Reference to Related Applications The present application claims priority from korean application No. 10-2024-0153982 filed on month 4 of 2024, 11, the entire contents of which are incorporated herein by reference. Technical Field Embodiments of the present disclosure relate generally to a memory device, and more particularly, to a memory device including a gate capping layer. Background Memory devices are of great interest as important elements in the electronics industry due to their characteristics such as miniaturization, versatility, and low manufacturing costs. As the electronic industry rapidly progresses, the integration of memory devices is increasing. In order to achieve high integration of the memory device, the line width of the wiring included in the memory device is gradually reduced, and the size of the memory cell becomes smaller. Due to this fact, the difficulty of the process for forming the memory cell is increasing. Disclosure of Invention Various embodiments of the present disclosure are directed to a memory device capable of preventing occurrence of process defects during a manufacturing process of the memory device. According to an embodiment of the present disclosure, a memory device may include a substrate including an active region, a word line embedded in the substrate and crossing the active region, a gate insulating layer surrounding side surfaces and a lower surface of the word line, a gate capping layer disposed on an inner side surface of the gate insulating layer on the word line, and a bit line contact contacting the active region disposed between the word lines and having a side surface facing the gate capping layer and recessed toward a center of the bit line contact. According to an embodiment of the present disclosure, a memory device may include a substrate including an active region, a word line embedded in the substrate and intersecting the active region, a gate insulating layer surrounding side and lower surfaces of the word line, a gate capping layer disposed on an inner side surface of the gate insulating layer on the word line, a buffer layer disposed on the gate capping layer, and a bit line contact including a first section and a second section in contact with the active region between the word line, the second section being located on and continuous with the first section, wherein an angle formed by the side surface of the first section and an upper surface of the substrate is different from an angle formed by the side surface of the second section and the upper surface of the substrate. According to embodiments of the present disclosure, a memory device may include a substrate including an active region, a bit line contact in contact with the active region, having a side surface recessed toward a center of the bit line contact, and including a first section and a second section on and continuous with the first section, a gate capping layer on the side surface of the first section of the bit line contact, and a buffer layer on the side surface of the second section of the bit line contact. According to the embodiments of the present disclosure, it is possible to prevent a process defect from occurring during a manufacturing process of a memory device. These and other features and advantages of the embodiments of the present disclosure will be better understood from the following embodiments in conjunction with the following description. Drawings Fig. 1 is a view showing a planar structure of a memory device according to an embodiment of the present disclosure. Fig. 2 is a view showing a cross-sectional structure taken along line I-I' of fig. 1. Fig. 3A is an enlarged view of portion 10 of fig. 2. Fig. 3B is another enlarged view of portion 10 of fig. 2. Fig. 4 is a view showing a cross-sectional structure taken along a line II-II' of fig. 1. Fig. 5 is a view showing a cross-sectional structure taken along line III-III' of fig. 1. Fig. 6 is a view showing another cross-sectional structure taken along line I-I' of fig. 1. Fig. 7A is an enlarged view of portion 20 of fig. 6. Fig. 7B is another enlarged view of portion 20 of fig. 6. Fig. 8 is a view showing another cross-sectional structure of a portion indicated by a line II-II' of fig. 1. Fig. 9 is a view showing another cross-sectional structure of a portion indicated by a line III-III' of fig. 1. Fig. 10 to 16 are views illustrating a method for forming a memory device according to an embodiment of the present disclosure. Fig. 17 to 20 are views illustrating another method for forming a memory device according to an embodiment of the present disclosure. Detailed Description Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. A specific structural or functional description of the embodiments is provided as an example to describe the technical concepts of the present disclosure. It should be noted, h