CN-122002797-A - Semiconductor device including through via

Abstract

A semiconductor device including a through via according to example embodiments of the present disclosure may include a first structure, and a second structure having a peripheral circuit region, and the first structure may include a memory cell, and a cell routing interconnect electrically connected to the memory cell, and the second structure may include a semiconductor body, a rear insulating layer disposed on a lower surface of the semiconductor body, a first peripheral transistor, a first through insulating pattern penetrating the semiconductor body, and a through via penetrating the first through insulating pattern and electrically connected to the cell routing interconnect, and the first through insulating pattern may include a first insulating pattern including a first portion adjacent to the rear insulating layer and a second portion disposed on the first portion, and a second insulating pattern disposed between a side surface of the second portion and the semiconductor body.

Inventors

• LI DINGLIE
• QUAN DONGHUI

Assignees

• 三星电子株式会社

Dates

Publication Date

20260508

Application Date

20250912

Priority Date

20241105

Claims (20)

1. 1. A semiconductor device, the semiconductor device comprising: a first structure having a storage area, and A second structure vertically overlapping the first structure and having a peripheral circuit region, Wherein the first structure comprises: a plurality of memory cells disposed within the memory region, each memory cell of the plurality of memory cells including a vertical channel transistor and an information storage structure, and A cell routing interconnect electrically connected to the plurality of memory cells, an Wherein the second structure comprises: a semiconductor body; a rear insulating layer located under the semiconductor body; A device isolation pattern defining a peripheral active region of the semiconductor body and having a lower surface at a vertical height greater than a vertical height of a lower surface of the semiconductor body; A first through insulation pattern penetrating the semiconductor body, the first through insulation pattern including a first portion and a second portion over the first portion, and a second insulation pattern between the second portion of the first insulation pattern and the semiconductor body and over the first portion of the first insulation pattern; A second through insulation pattern penetrating the device isolation pattern and the semiconductor body under the device isolation pattern; A peripheral transistor including first and second peripheral source/drains disposed within the peripheral active region, a peripheral channel region between the first and second peripheral source/drains, and a peripheral gate disposed on the peripheral channel region, and A through via penetrating the first through insulation pattern and electrically connected to the cell routing interconnect line.
2. 2. The semiconductor device according to claim 1, Wherein a lower surface of the semiconductor body, a lower surface of the first through insulation pattern, and a lower surface of the second through insulation pattern are coplanar with each other.
3. 3. The semiconductor device according to claim 1, Wherein an upper surface of the first through insulation pattern, an upper surface of the second through insulation pattern, and an upper surface of the semiconductor body are coplanar with each other.
4. 4. The semiconductor device according to claim 1, Wherein the first portion is adjacent to the rear insulating layer and the second portion extends upward from the first portion, and The first portion of the first insulating pattern separates the second insulating pattern from the rear insulating layer.
5. 5. The semiconductor device according to claim 4, Wherein the first insulating pattern comprises a first insulating material, and The second insulating pattern includes a second insulating material different from the first insulating material.
6. 6. The semiconductor device according to claim 4, Wherein an upper surface of the first portion of the first insulating pattern includes a first region and a second region other than the first region, the second portion of the first insulating pattern extending from the first region, and The second region of the upper surface of the first portion is in contact with the semiconductor body.
7. 7. The semiconductor device according to claim 1, Wherein the lower surface of the first through insulating pattern has a first width in a first direction, and The lower surface of the second through insulation pattern has a second width smaller than the first width in the first direction.
8. 8. The semiconductor device according to claim 1, Wherein the second through insulation pattern includes: a third insulating pattern including a third portion adjacent to the rear insulating layer and a fourth portion over and extending from the third portion, and A fourth insulating pattern located between the fourth portion of the third insulating pattern and the semiconductor body and over the third portion of the third insulating pattern.
9. 9. The semiconductor device according to claim 8, Wherein an upper surface of the third portion of the third insulating pattern includes a third region and a fourth region other than the third region, the fourth portion of the third insulating pattern extending from the third region, and The fourth region of the upper surface of the third portion is in contact with the semiconductor body.
10. 10. The semiconductor device according to claim 8, Wherein a lower surface of the fourth insulation pattern of the second through insulation pattern is at a lower vertical height than a lower surface of the device isolation pattern.
11. 11. The semiconductor device according to claim 1, Wherein the device isolation pattern includes a first device isolation insulating film, a second device isolation insulating film in contact with side surfaces and lower surfaces of the first device isolation insulating film, and a third device isolation insulating film in contact with side surfaces and lower surfaces of the second device isolation insulating film, The first device isolation insulating film and the third device isolation insulating film include a third insulating material, and The second device isolation insulating film includes a fourth insulating material different from the third insulating material.
12. 12. The semiconductor device according to claim 11, Wherein the first through insulating pattern includes a first through insulating film, a second through insulating film in contact with a side surface and a lower surface of the first through insulating film, and a third through insulating film in contact with a side surface and a lower surface of the second through insulating film, The first through insulating film and the third through insulating film include the third insulating material, and The second through insulating film includes the fourth insulating material.
13. 13. A semiconductor device, the semiconductor device comprising: a first structure having a storage area, and A second structure vertically overlapping the first structure and having a peripheral circuit region, Wherein the first structure comprises: A plurality of memory cells disposed within the memory area, and A cell routing interconnect electrically connected to the plurality of memory cells, an Wherein the second structure comprises: a semiconductor body; a rear insulating layer disposed on a lower surface of the semiconductor body; a first peripheral transistor including first and second peripheral source/drains disposed within a first peripheral active region of the semiconductor body, a first peripheral channel region between the first and second peripheral source/drains, and a first peripheral gate disposed on the first peripheral channel region; a first through insulation pattern penetrating the semiconductor body; A device isolation pattern having a lower surface in a vertical height higher than a lower surface of the semiconductor body and spaced apart from the first through insulation pattern in a horizontal direction within the semiconductor body, and A through via penetrating the first through insulation pattern and the rear insulation layer and electrically connected to the cell routing interconnection line, Wherein the first through insulation pattern includes a first insulation pattern including a first portion adjacent to the rear insulation layer and a second portion disposed on the first portion, and a second insulation pattern disposed between a side surface of the second portion of the first insulation pattern and the semiconductor body.
14. 14. The semiconductor device according to claim 13, Wherein a side surface of the first portion of the first insulating pattern is in contact with the semiconductor body.
15. 15. The semiconductor device according to claim 13, Wherein the first insulating pattern comprises silicon oxide, and The second insulating pattern includes silicon nitride.
16. 16. The semiconductor device according to claim 13, Wherein the device isolation pattern includes a first device isolation insulating film, a second device isolation insulating film in contact with side surfaces and lower surfaces of the first device isolation insulating film, and a third device isolation insulating film in contact with side surfaces and lower surfaces of the second device isolation insulating film, The first insulating pattern, the first device isolation insulating film, and the third device isolation insulating film of the first through insulating pattern include a first insulating material, and The second insulating pattern of the first through insulating pattern and the second device isolation insulating film include a second insulating material different from the first insulating material.
17. 17. The semiconductor device according to claim 13, Wherein the second structure further comprises: A second peripheral transistor including third and fourth peripheral source/drains disposed within a second peripheral active region of the semiconductor body, a second peripheral channel region between the third and fourth peripheral source/drains, and a second peripheral gate disposed on the second peripheral channel region of the second peripheral active region, an The device isolation pattern is disposed between the first peripheral transistor and the second peripheral transistor.
18. 18. The semiconductor device according to claim 13, Wherein the second structure further comprises a second through insulation pattern penetrating the device isolation pattern and penetrating the semiconductor body under the device isolation pattern, and The second through insulation pattern includes: A third insulating pattern including a third portion located above and adjacent to the rear insulating layer and a fourth portion extending from the third portion, and A fourth insulating pattern located between the fourth portion of the third insulating pattern and the semiconductor body and over the third portion of the third insulating pattern.
19. 19. A semiconductor device, the semiconductor device comprising: a first structure having a plurality of memory cells disposed in a memory region and cell routing interconnect electrically connected to the plurality of memory cells, and A second structure vertically overlapping the first structure and having a peripheral circuit region, Wherein the second structure comprises: a semiconductor body; A device isolation pattern defining a peripheral active region of the semiconductor body; a first through insulation pattern penetrating the semiconductor body; A peripheral transistor including first and second peripheral source/drains disposed within the peripheral active region, a peripheral channel region between the first and second peripheral source/drains, and a peripheral gate disposed on the peripheral channel region, and A through via penetrating the first through insulating pattern and electrically connected to the cell routing interconnect line, an The first through insulating pattern includes a first insulating pattern having a first portion having a lower surface coplanar with a lower surface of the semiconductor body and a second portion disposed on the first portion, and a second insulating pattern on a side surface of the second portion of the first insulating pattern.
20. 20. The semiconductor device of claim 19, Wherein a first height of the first portion of the first insulation pattern in a vertical direction is smaller than a second height of the second portion of the first insulation pattern in the vertical direction.

Description

Semiconductor device including through via Technical Field The present disclosure relates to a semiconductor device including a through via. Background In order to reduce the size of elements included in a semiconductor device and improve the performance thereof, research is being conducted. For example, in a DRAM, research is being conducted for reliably and stably forming elements of a reduced size, but the performance of a semiconductor device is always degraded as the size of the elements is reduced. Disclosure of Invention An aspect of the present disclosure is to provide a device with improved reliability. However, the object of the present invention is not limited to the above object, and may be variously extended without departing from the spirit and scope of the present disclosure. The semiconductor device according to example embodiments of the present disclosure may include a first structure having a memory region; and a second structure vertically overlapping the first structure and having a peripheral circuit region, and the first structure may include a plurality of memory cells disposed within the memory region, each of the plurality of memory cells including a vertical channel transistor and an information storage structure, and a cell routing interconnect electrically connected to the plurality of memory cells, and the second structure may include a semiconductor body, a rear insulating layer under the semiconductor body, a device isolation pattern defining a peripheral active region of the semiconductor body and having a lower surface at a vertical height higher than a vertical height of a lower surface of the semiconductor body, the device isolation pattern including a first device isolation pattern, a first through insulating pattern penetrating the semiconductor body, the first through insulating pattern including a first insulating pattern and a second insulating pattern, the first insulating pattern including a first portion and a second portion over the first portion, the second insulating pattern being located between the first insulating pattern and the first peripheral transistor, the first through insulating pattern including a first transistor, the first through the peripheral transistor, the first through insulating pattern including a first through the first through insulating pattern, and a peripheral channel region between the first and second peripheral source/drains and a peripheral gate disposed on the peripheral channel region, and a through via penetrating the first through insulation pattern and electrically connected to the cell routing interconnection line. The semiconductor device according to example embodiments of the present disclosure may include a first structure having a memory region, and a second structure vertically overlapping the first structure and having a peripheral circuit region, and the first structure may include a plurality of memory cells disposed within the memory region, and a cell routing interconnect electrically connected to the plurality of memory cells, and the second structure may include a semiconductor body, a rear insulating layer disposed on a lower surface of the semiconductor body, a first peripheral transistor including first and second peripheral source/drain electrodes disposed within a first peripheral active region of the semiconductor body, a first peripheral channel region between the first and second peripheral source/drain electrodes, and a first peripheral gate electrode disposed on the first peripheral channel region, a first through-via pattern within the semiconductor body having a first through-via pattern at a height above the lower surface of the semiconductor body and electrically separated from the first insulating layer by a first through-via pattern and a second insulating layer, the first through-via pattern may be disposed adjacent to the first insulating layer and the first insulating layer in a horizontal direction, the second insulating pattern is disposed between a side surface of the second portion of the first insulating pattern and the semiconductor body. The semiconductor device according to example embodiments may include a first structure having a plurality of memory cells disposed in a memory region and a cell routing interconnect line electrically connected to the plurality of memory cells, and a second structure vertically overlapping the first structure and having a peripheral circuit region, and the second structure may include a semiconductor body, a device isolation pattern defining a peripheral active region of the semiconductor body, a first through insulation pattern penetrating the semiconductor body, a peripheral transistor including first and second peripheral source/drain electrodes disposed within the peripheral active region, a peripheral channel region between the first and second peripheral source/drain electrodes, and a peripheral gate electrode disposed on the peripheral channel re