CN-122002798-A - Memory circuitry and method for forming memory circuitry

Abstract

The present disclosure relates to memory circuitry and methods for forming memory circuitry. The memory circuitry includes an integrated circuit die that includes a radially outermost region surrounding a radially inner region. The inner region includes a memory array region. The radially outermost region includes a lower semiconductor material, an insulating material directly above the lower semiconductor material, and a stack including alternating levels of different constituent semiconductive materials directly above the insulating material. An electrically conductive wall is configured in the radially outermost region to at least partially surround the inner region. Other embodiments are disclosed that include methods.

Inventors

• P. V.K. Nitara
• YOKOYAMA YUICHI
• LI BENBEN
• M. BALAKRISHNAN
• K. Astrebetsky

Assignees

• 美光科技公司

Dates

Publication Date

20260508

Application Date

20250928

Priority Date

20250910

Claims (20)

1. 1. A memory circuitry, comprising: an integrated circuit die comprising a radially outermost region surrounding a radially inner region, the radially inner region comprising a memory array region including memory cells, the radially outermost region comprising: a lower semiconductor material; An insulating material directly above the lower semiconductor material, and A stack comprising alternating levels of different composition semiconductive materials directly above the insulating material, and A conductive wall construction in the radially outermost region at least partially surrounding the radially inner region, the conductive wall construction extending through the stack and the insulating material to the lower semiconductor material, the conductive wall construction comprising two lateral outer regions of insulating material having a conductive core laterally therebetween, the conductive core being directly electrically coupled to the lower semiconductor material.
2. 2. The memory circuitry of claim 1, wherein the conductive wall configuration completely surrounds the radially inner region.
3. 3. The memory circuitry of claim 1, wherein the memory cells are vertically stacked in the memory array region and individually comprise capacitors and horizontal transistors.
4. 4. The memory circuitry of claim 1, wherein one of the different constituent semiconductive materials comprises silicon and the other comprises a silicon germanium alloy.
5. 5. The memory circuitry of claim 4, wherein the silicon is at least twice as thick as the silicon germanium alloy.
6. 6. The memory circuitry of claim 1, wherein the lower semiconductor material comprises silicon.
7. 7. The memory circuitry of claim 1, wherein the insulating material comprises silicon dioxide.
8. 8. The memory circuitry of claim 1, wherein: The memory cells are vertically stacked in the memory array region and individually comprise capacitors and horizontal transistors; One of the different constituent semiconductive materials comprises silicon and the other comprises a silicon germanium alloy; The lower semiconductor material comprises silicon, and The insulating material comprises silicon dioxide.
9. 9. The memory circuitry of claim 1, wherein the two lateral outer regions of insulating material terminate over or in the insulating material.
10. 10. The memory circuitry of claim 1, wherein the conductive core comprises two laterally outer regions of a first conductive material and a laterally inner region of a second conductive material laterally intermediate the two laterally outer regions, the first and second conductive materials having different compositions relative to one another.
11. 11. The memory circuitry of claim 1, comprising two of the conductive wall formations in the radially outermost region, the two conductive wall formations being laterally spaced from one another in the stack.
12. 12. The memory circuitry of claim 11, wherein the conductive cores of the two conductive wall structures are directly against each other in the lower semiconductor material.
13. 13. A memory circuitry, comprising: an integrated circuit die including a radially outermost region surrounding a radially inner region; The radially inner region includes a memory array region and an adjacent region horizontally adjacent to the memory array region, the memory array region including a vertically alternating insulating layer and a memory cell layer including memory cells individually including horizontal transistors including gates including portions of one of a plurality of horizontal conductive access lines individually electrically coupling together and extending horizontally from the memory array region into the adjacent region a plurality of the gates of different ones of the horizontal transistors in the same memory cell layer; The radially outermost region includes: a lower semiconductor material; An insulating material directly above the lower semiconductor material, and A stack comprising alternating levels of different constituent semiconductive materials directly above the insulating material; A conductive wall configuration in the radially outermost region to at least partially surround the radially inner region; Conductive via structures in the adjacent regions, individually electrically coupled directly to individual ones of the access lines; The conductive wall structure extending through the stack and the insulating material to the lower semiconductor material, the conductive wall structure comprising two lateral outer regions of insulating material having a conductive core material laterally therebetween, the conductive core material being directly electrically coupled to the lower semiconductor material, and The conductive via configuration individually includes a conductive core having the same conductive core material as the conductive wall configuration and a radially outer insulating liner circumferentially surrounding the conductive core having the same insulating material as the two lateral outer regions of the conductive wall configuration.
14. 14. The memory circuitry of claim 13, wherein the conductive core material comprises first and second conductive materials having different compositions relative to each other.
15. 15. The memory circuitry of claim 14, wherein: in the conductive wall configuration, the first conductive material is in two laterally outer regions laterally outward of the laterally inner region of the second conductive material, and In the conductive via configuration, the first conductive material is in a radially outer region directly against the radially outer insulating liner and radially outward of the second conductive material.
16. 16. The memory circuitry of claim 15, wherein the first conductive material is titanium nitride and the second conductive material is elemental tungsten.
17. 17. The memory circuitry of claim 16, wherein the insulating material is silicon nitride.
18. 18. The memory circuitry of claim 13, wherein the two lateral outer regions of insulating material terminate over or in the insulating material.
19. 19. A memory circuitry, comprising: an integrated circuit die including a radially outermost region surrounding a radially inner region; The radially inner region includes a memory array region including memory cells individually including capacitors; The radially outermost region includes: a lower semiconductor material; An insulating material directly above the lower semiconductor material, and A stack comprising alternating levels of different constituent semiconductive materials directly above the insulating material; A conductive wall configuration in the radially outermost region to at least partially surround the radially inner region; the capacitor includes a conductive storage node electrode, a conductive cell plate electrode including a conductive material, and A capacitor insulator comprising insulator material between the conductive storage node electrode and the conductive cell plate electrode, an The conductive wall construction extends through the stack and the insulating material to the lower semiconductor material, the conductive wall construction including two lateral outer regions of insulating material having a conductive core material laterally therebetween, the conductive core material being directly electrically coupled to the lower semiconductor material, the conductive core material having the same conductive material as the cell plate electrode.
20. 20. The memory circuitry of claim 19, wherein the conductive material comprises a conductively doped semiconductive material.

Description

Memory circuitry and method for forming memory circuitry Technical Field Embodiments disclosed herein relate to memory circuitry and methods for forming memory circuitry. Background Memory is a type of integrated circuit system and is used in computer systems to store data. The memory may be fabricated as one or more arrays of individual memory cells. Memory cells may be written or read using digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines). The sense lines can conductively interconnect memory cells along columns of the array, and the access lines can conductively interconnect memory cells along rows of the array. Each memory cell is uniquely addressable by a combination of sense lines and access lines. The memory cells may be volatile, semi-volatile, or nonvolatile. Nonvolatile memory cells can store data for long periods of time without power. Nonvolatile memory is typically designated as memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of a few milliseconds or less. Regardless, the memory cells are configured to retain or store memory with at least two different selectable states. In binary systems, the state is considered to be either a "0" or a "1". In other systems, at least some individual memory cells may be configured to store more than two levels or states of information. The memory cells may be arranged or arrayed in a number of ways, including substantially horizontal in a single plane or alternatively, such as in a vertical stack (e.g., in the z-direction) that includes a three-dimensional (3D) memory array region having a horizontal hierarchy in which individual memory cells are received (e.g., arrayed in the x-and y-directions). The stack in the 3D memory array region includes vertically alternating insulating and conductive levels extending into the stair-step region (e.g., as part of the memory cell levels). The stair-step regions include individual "steps" (alternatively referred to as "rungs" or "steps") that define contact regions of conductive lines of individual ones of the conductive levels with which vertical conductive vias may contact to provide electrical pathways to and from these conductive lines. Disclosure of Invention In one aspect, the present disclosure provides a memory circuitry comprising an integrated circuit die comprising a radially outermost region surrounding a radially inner region, the radially inner region comprising a memory array region including memory cells, the radially outermost region comprising a lower semiconductor material, an insulating material directly above the lower semiconductor material, and a stack comprising alternating layers of different constituent semiconductive materials directly above the insulating material, and a conductive wall construction in the radially outermost region to at least partially surround the radially inner region, the conductive wall construction extending through the stack and the insulating material to the lower semiconductor material, the conductive wall construction comprising two lateral outer regions of insulating material having a conductive core laterally therebetween, the conductive core being directly electrically coupled to the lower semiconductor material. In another aspect, the present disclosure provides a memory circuit system comprising an integrated circuit die comprising a radially outermost region surrounding a radially inner region, the radially inner region comprising a memory array region and an adjacent region horizontally adjacent to the memory array region, the memory array region comprising a vertical alternating insulating layer and a memory cell layer, the memory cell layer comprising memory cells, the memory cells individually comprising horizontal transistors including gates comprising portions of one of a plurality of horizontal conductive access lines individually electrically coupling together a plurality of the gates of different ones of the horizontal transistors in the same memory cell layer and extending horizontally from the memory array region into the adjacent region, the radially outermost region comprising a lower semiconductor material, an insulating material layer directly above the lower semiconductor material, and a stack comprising alternating conductive wall structures of different constituent semiconductor materials directly above the insulating material, at least partially surrounding the radially outermost region, electrically coupling together a plurality of the gates of different ones of the horizontal transistors in the same memory cell layer and extending horizontally from the memory array region into the adjacent region, the radially outermost region comprising a conductive liner electrically coupling between the respective cond