CN-122002799-A - Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device is disclosed that includes a first gate extending in a first direction, an island-shaped gate adjacent to one end of the first gate in the first direction, a second gate spaced apart from the first gate in a second direction perpendicular to the first direction and extending in the first direction, and a contact plug in contact with the island-shaped gate and the second gate.

Inventors

• LI LIANGUI
• Cheng Minzhe
• LIU CHENGYU

Assignees

• 爱思开海力士有限公司

Dates

Publication Date

20260508

Application Date

20251016

Priority Date

20241106

Claims (20)

1. 1. A semiconductor device, comprising: a first gate configured to extend in a first direction; an island-shaped gate adjacent to one end of the first gate in the first direction; a second gate spaced apart from the first gate in a second direction perpendicular to the first direction and configured to extend along the first direction, and And a contact plug in contact with the island-shaped gate and the second gate.
2. 2. The semiconductor device of claim 1, wherein the island-like gate has a quadrilateral shape.
3. 3. The semiconductor device of claim 2, wherein the second gate surrounds at least three sides of the island gate.
4. 4. The semiconductor device according to claim 1, wherein the second gate includes a bridge portion provided between the island-shaped gate and the first gate.
5. 5. The semiconductor device of claim 1, wherein the second gate is in contact with the island gate.
6. 6. The semiconductor device of claim 1, further comprising: A bit line spaced apart from the first gate in a third direction perpendicular to the first direction and the second direction and configured to extend along the second direction.
7. 7. The semiconductor device of claim 6, further comprising: an active region, the active region being in contact with the bit line, Wherein the active region includes a horizontal portion in contact with the bit line and configured to extend in the second direction, and a vertical portion configured to extend in the third direction.
8. 8. The semiconductor device of claim 7, wherein the vertical portion is disposed between the first gate and the second gate.
9. 9. The semiconductor device according to claim 8, wherein the first gate is disposed between the vertical portions respectively included in adjacent active regions.
10. 10. The semiconductor device according to claim 8, wherein the active region comprises an oxide semiconductor.
11. 11. The semiconductor device of claim 1, further comprising: And an isolation region configured to isolate adjacent second gates from each other.
12. 12. The semiconductor device of claim 11, wherein the isolation region is disposed between the first gate and the island gate.
13. 13. The semiconductor device according to claim 11, wherein the isolation region is in contact with one end portion of the second gate in the first direction.
14. 14. The semiconductor device of claim 1, wherein a voltage provided to the first gate is different from a voltage provided to the second gate.
15. 15. The semiconductor device of claim 14, wherein the voltage provided to the first gate is a ground voltage.
16. 16. The semiconductor device of claim 1, further comprising: another island-shaped gate adjacent to an opposite end of the first gate in the first direction, and And another contact plug electrically connected to the another island-shaped gate.
17. 17. The semiconductor device according to claim 16, wherein the contact plug and the other contact plug are disposed in a diagonal direction with respect to a center of the first gate.
18. 18. A semiconductor device, comprising: a first gate configured to extend in a first direction; A bit line configured to extend in a second direction perpendicular to the first direction; a second gate spaced apart from the first gate in the second direction; An active region including a horizontal portion in contact with the bit line, and a vertical portion configured to extend in a third direction perpendicular to the first direction and the second direction; An island-shaped gate adjacent to one end of the first gate in the first direction, and A contact plug configured to overlap the island-shaped gate and the second gate, Wherein the vertical portion is disposed between the first gate and the second gate.
19. 19. The semiconductor device of claim 18, further comprising: And an isolation region configured to isolate adjacent second gates from each other.
20. 20. A semiconductor device, comprising: a first gate and a second gate extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction, and An island-shaped gate adjacent to a first end of the first gate; Wherein the second gate surrounds three sides of the island gate, and Wherein the second gate includes a bridge portion disposed between the island gate and the first gate.

Description

Semiconductor device and method for manufacturing the same Cross Reference to Related Applications The present application claims priority from korean patent application No. 10-2024-0156248 filed on 11/6 of 2024, the entire disclosure of which is incorporated herein by reference. Technical Field Embodiments of the present disclosure relate generally to a semiconductor device, and more particularly, to a semiconductor device including a memory cell. Background Since the improvement of the compactness of the semiconductor device and the integration thereof has emerged as a major problem, the memory cells included in the semiconductor device may be formed to have a three-dimensional pattern, and the operation characteristics of the memory cells may be improved. As semiconductor devices become more compact and highly integrated, memory cells within these semiconductor devices are increasingly designed to have a three-dimensional structure. This 3D configuration enhances the operational performance of the memory cells, helps overcome the limitations of conventional 2D layout and supports advances in modern chip technology. Because of the relatively recent nature of these 3D structures, ongoing research is focused on improving their structural integrity, reliability, and overall performance characteristics. Disclosure of Invention Embodiments of the present disclosure are directed to solving the problems occurring in the prior art, while the advantages achieved by the prior art remain unchanged. According to an embodiment of the present disclosure, a three-dimensional semiconductor device (hereinafter simply referred to as a semiconductor device) is provided, which exhibits improved integration in other improvements. The semiconductor device according to the embodiment may include an island-shaped gate to improve contact stability between a gate included in the semiconductor device and a contact plug. Further, the semiconductor device of the present disclosure may include an island-shaped gate connected to the contact plug to ensure a margin of forming the contact plug and reduce process difficulty. It is noted that technical problems solved by the embodiments of the present disclosure are not limited to the above-described problems, and other technical problems not mentioned herein will be apparent to those of ordinary skill in the art to which the present disclosure pertains from the following description. According to an embodiment of the present disclosure, a semiconductor device includes a first gate extending in a first direction, an island-shaped gate adjacent to one end of the first gate in the first direction, a second gate spaced apart from the first gate in a second direction perpendicular to the first direction and extending in the first direction, and a contact plug contacting the island-shaped gate and the second gate. According to an embodiment, the island-shaped gate may have a quadrangular shape, and the second gate may surround at least three sides of the island-shaped gate. According to an embodiment, the second gate may include a bridge portion disposed between the island gate and the first gate. According to an embodiment, the second gate may be in contact with the island-shaped gate. According to an embodiment, the semiconductor device may further include a bit line spaced apart from the first gate in a third direction perpendicular to the first direction and the second direction and extending in the second direction. According to an embodiment, the semiconductor device may further include an active region in contact with the bit line, and the active region includes a horizontal portion in contact with the bit line and extending in the second direction, and a vertical portion extending in the third direction. According to an embodiment, the vertical portion may be disposed between the first gate and the second gate. According to an embodiment, the first gate electrode may be disposed between vertical portions respectively included in adjacent active regions. According to an embodiment, the active region may include an oxide semiconductor. According to an embodiment, the semiconductor device may further include an isolation region isolating adjacent second gates from each other. According to an embodiment, an isolation region may be provided between the first gate and the island gate. According to an embodiment, the isolation region may be in contact with one end of the second gate in the first direction. According to an embodiment, the voltage provided to the first gate may be different from the voltage provided to the second gate. According to an embodiment, the voltage supplied to the first gate may be a ground voltage. According to an embodiment, the semiconductor device may further include another island-shaped gate adjacent to an opposite end of the first gate in the first direction, and another contact plug electrically connected to the another island-shaped gate. According to an embod