CN-122002800-A - Digital line formation in vertical three-dimensional (3D) memory

CN122002800ACN 122002800 ACN122002800 ACN 122002800ACN-122002800-A

Abstract

The present disclosure relates to digit line formation in vertical three-dimensional 3D memories. Systems, methods, and apparatus are provided for a vertically stacked array of memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access device has a first source/drain region and a second source/drain region separated by a channel region. The gate at the channel region forms a fully surrounding gate GAA structure completely surrounding each surface of the channel region as separated from the channel region by a gate dielectric. The memory cell has a horizontally oriented storage node connected to the second source/drain region and a digit line connected to the first source/drain region.

Inventors

G. Mususami
D.V.N. Ramaswamy
A. Malik
H.A. Abbas
ZHAO XIAOHUI
J.F. Ke Ding
MA YUANZHI
ZHAO TING
A.Liao
S. M.I. Hussein
S.E. Syris

Assignees

美光科技公司

Dates

Publication Date: 20260508
Application Date: 20251030
Priority Date: 20241104

Claims (15)

1. A method for forming a three-dimensional 3D memory, comprising: Forming a vertical stack from a substrate having alternating layers of silicon germanium (SiGe) material and silicon (Si) material, the vertical stack having vertically stacked memory cells having horizontally oriented access devices having gates, channel regions, first and second source/drain regions separated by the channel regions, and horizontally oriented storage nodes, formed horizontally at different levels from one another; Forming a first vertical opening through the vertical stack and extending primarily in a first horizontal direction to expose a first vertical sidewall in the stack; Three-dimensionally recessing surrounding material from the Si material in the exposed first vertical sidewall to create a three-dimensional exposed surface on the Si material; Epitaxially growing a Si material from the three-dimensional exposed Si material to form an enlarged epitaxially grown Si material contact having a cross-sectional dimension greater than an original cross-sectional dimension of the Si material; forming a plurality of spaced vertical pillars between the Si material contacts in the first vertical opening, and A conductive material is deposited between the plurality of spaced vertical pillars to form a plurality of spaced vertical digit lines in the first vertical opening electrically connected to the first source/drain region.
2. The method of claim 1, wherein the method includes epitaxially growing the Si material a specific amount to form the enlarged Si material contacts such that the enlarged Si material contacts are electrically isolated from each other.
3. The method of claim 1, wherein the method includes epitaxially growing the Si material to form the enlarged Si material contact having a graded doping concentration.
4. The method of claim 1, wherein the method comprises: Depositing a first dielectric material in the first vertical opening to fill the first vertical opening; patterning a mask on top of the vertical stack, and Portions of the first dielectric material in the first vertical openings are selectively removed to form a plurality of spaced vertical openings between the plurality of spaced vertical pillars, wherein selectively removing the portions of the first dielectric material exposes the enlarged Si material contacts in the plurality of spaced vertical openings.
5. The method of claim 4, wherein the method includes depositing the conductive material in the plurality of spaced vertical openings to form the plurality of spaced vertical digit lines.
6. The method of claim 1, wherein epitaxially growing the Si material includes epitaxially growing a plurality of layers of Si material from the three-dimensional exposed Si material.
7. The method of claim 6, wherein epitaxially growing the plurality of layers of the Si material comprises: epitaxially growing a first layer of the plurality of layers of the Si material to have a first thickness, and A second layer of the plurality of layers of the Si material is epitaxially grown to have a second thickness less than the first thickness of the first layer to control a gate-to-vertical digit line contact separation distance.
8. The method of claim 7, wherein the method includes epitaxially growing the first layer to have a first doping concentration and epitaxially growing the second layer to have a second doping concentration different from the first doping concentration.
9. The method of claim 7, wherein the method comprises: epitaxially growing the first layer to have a thickness between 1nm and 20 nm a The second layer is epitaxially grown to have a thickness between 1 nm and 20 a nm a.
10. The method of claim 1, wherein forming the horizontally oriented access device and the horizontally oriented storage node at each level of the vertical stack comprises: Forming a plurality of second vertical openings through the vertical stack having a first horizontal direction and a second horizontal direction, the second vertical openings extending primarily in the second horizontal direction to form elongated vertical pillars in the stack having first vertical sidewalls separating memory cells on each level; Doping the first source/drain region of the Si layer at the second vertical opening; Depositing a first dielectric in the plurality of second vertical openings, and A third vertical opening is formed through the vertical stack and extending primarily in the first horizontal direction to expose a second vertical sidewall in the stack.
11. The method of claim 10, wherein forming the horizontally oriented access device and the horizontally oriented storage node at each level of the vertical stack further comprises: Selectively etching the silicon germanium (SiGe) layer and reducing a vertical thickness of the Si layer to form a plurality of first horizontal openings of a first length (L1) from the third vertical opening; conformally depositing a second dielectric material on exposed surfaces in the plurality of first horizontal openings; recessing the second dielectric material to expose the first source/drain regions; depositing the first dielectric material to fill the plurality of first horizontal openings; Selectively etching the second dielectric material from the plurality of first horizontal openings to a second length (L2) from the second vertical openings; Forming a gate dielectric material on the reduced vertical thickness exposed surface of the Si layer; depositing a first conductive material on the Si layer to form a fully-surrounding gate GAA structure at the channel region of the access device; recessing the first conductive material into the channel region, and The first horizontal opening is capped with the second dielectric material.
12. A method for forming a three-dimensional 3D memory, comprising: Forming a vertical stack from a substrate having alternating layers of silicon germanium (SiGe) material and silicon (Si) material, the vertical stack having vertically stacked memory cells having horizontally oriented access devices having gates, channel regions, first and second source/drain regions separated by the channel regions, and horizontally oriented storage nodes, formed horizontally at different levels from one another; Forming a first vertical opening through the vertical stack and extending primarily in a first horizontal direction to expose a first vertical sidewall in the stack; Three-dimensionally recessing surrounding material from the Si material in the exposed first vertical sidewall to create a three-dimensional exposed surface on the Si material; Epitaxially growing a gradient doped Si material from the three-dimensional exposed Si material to form an enlarged epitaxially grown Si material contact having a cross-sectional dimension greater than an original cross-sectional dimension of the Si material; forming a plurality of spaced vertical pillars having a plurality of spaced vertical openings therebetween, wherein the enlarged Si material contacts are located in the plurality of spaced vertical openings, and A conductive material is deposited in the plurality of spaced apart vertical openings to form a plurality of spaced apart vertical digit lines in the first vertical opening electrically connected to the first source/drain region.
13. The method of claim 12, wherein the method comprises: Depositing a first dielectric material in the first vertical opening to fill the first vertical opening; patterning a mask on top of the vertical stack, and Portions of the first dielectric material in the first vertical openings are selectively removed to form the plurality of spaced vertical openings between the plurality of spaced vertical pillars.
14. A memory device, comprising: A vertically stacked array of memory cells having a horizontally oriented access device and a horizontally oriented storage node, wherein: the horizontally oriented access device includes a channel region, a first source/drain region separated by the channel region, a second source/drain region, and a gate on a gate dielectric material, an The horizontally oriented storage node being formed horizontally on the second source/drain region of the horizontally oriented access device, and A vertical digit line having a gradient doped enlarged Si material contact and a conductive material deposited in a plurality of vertical openings, wherein the vertical digit line is connected to the first source/drain region of the horizontally oriented access device.
15. The memory device of claim 14, wherein the array comprises horizontally oriented access lines formed to the gates of the horizontally oriented access devices.

Description

Digital line formation in vertical three-dimensional (3D) memory Technical Field The present disclosure relates generally to memory devices, and more particularly, to digit line formation in vertical three-dimensional (3D) memory. Background The memory is typically implemented in electronic systems such as computers, cell phones, hand-held devices, etc. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data and may include Random Access Memory (RAM), dynamic Random Access Memory (DRAM), static Random Access Memory (SRAM), and Synchronous Dynamic Random Access Memory (SDRAM). Nonvolatile memory may provide persistent data by retaining stored data when unpowered and may include NAND flash memory, NOR flash memory, nitride Read Only Memory (NROM), phase change memory (e.g., phase change random access memory), resistive memory (e.g., resistive random access memory), cross point memory, ferroelectric random access memory (FeRAM), or the like. As design rules shrink, less semiconductor space is available for manufacturing memories including DRAM arrays. The respective memory cell of the DRAM may include an access device, such as a transistor, having first and second source/drain regions separated by an epitaxially grown channel region. The gate may be opposite the channel region and separated from the channel region by a gate dielectric. An access line (e.g., a word line) is electrically connected to the gates of the DRAM cells. The DRAM cell may include a storage node, such as a capacitor cell, connected to the digit line through an access device. The access device may be activated (e.g., for selecting a cell) by an access line connected to the access transistor. The capacitor may store a charge corresponding to a data value (e.g., a logic "1" or "0") of the respective cell. Disclosure of Invention In one aspect, the present disclosure provides a method for forming a three-dimensional (3D) memory comprising forming a vertical stack of alternating layers of silicon germanium (SiGe) material and silicon (Si) material from a substrate, the vertical stack having vertically stacked memory cells with horizontally oriented access devices having gates, channel regions, first source/drain regions and second source/drain regions formed horizontally at different levels from each other, forming a first vertical opening extending primarily in a first horizontal direction through the vertical stack to expose a first vertical sidewall in the stack, three-dimensionally recessing surrounding material from the Si material in the exposed first vertical sidewall to create a three-dimensional exposed surface on the Si material, epitaxially growing Si material from the three-dimensional exposed Si material to form an enlarged epitaxially grown Si material contact having a cross-sectional dimension greater than an original cross-sectional dimension of the Si material, forming a plurality of spaced vertical pillars between the Si material contacts in the first vertical opening, and forming a plurality of vertical spacers connected to the first conductive lines in the first vertical openings. In another aspect, the present disclosure provides a method for forming a three-dimensional (3D) memory comprising forming a vertical stack of alternating layers of silicon germanium (SiGe) material and silicon (Si) material from a substrate, the vertical stack having vertically stacked memory cells with horizontally oriented access devices having gates, channel regions, first source/drain regions and second source/drain regions formed horizontally at different levels from each other, forming a first vertical opening extending primarily in a first horizontal direction through the vertical stack to expose a first vertical sidewall in the stack, three-dimensionally recessing surrounding material from the Si material in the exposed first vertical sidewall to create a three-dimensional exposed surface on the Si material, epitaxially growing gradient doped Si material from the three-dimensional exposed Si material to form a plurality of spaced apart vertical pillars having cross-sectional dimensions greater than the original cross-sectional dimensions of the Si material, formed in between them, wherein the Si material is located in the plurality of vertical openings and the plurality of spaced apart vertical pillars are electrically connected to the plurality of conductive lines in the first vertical openings. In another aspect, the disclosure provides a memory device comprising an array of vertically stacked memory cells having a horizontally oriented access device and a horizontally oriented storage node, wherein the horizontally oriented access device includes a channel region, a first source/drain region, a second source/drain region, and a gate on a gate dielectric material separated by the channel region, and the horizontally oriented storage node is formed horizont