CN-122002801-A - Transistor device with selective thick gate dielectric and method

Abstract

The present disclosure relates to transistor devices and methods having selective thick gate dielectrics. Apparatus and methods including transistors, semiconductor devices, and systems are disclosed. Example semiconductor devices and methods include gate dielectrics having different thicknesses in transistor devices. Apparatus and methods are disclosed that use dopants to alter the growth of a gate dielectric at a desired location within a semiconductor device.

Inventors

• M. S. Bor
• S. S. Mujiondar
• U. SHARMA

Assignees

• 美光科技公司

Dates

Publication Date

20260508

Application Date

20251104

Priority Date

20241106

Claims (20)

1. 1. A semiconductor memory device, comprising: a transmission line having a width and a thickness between a top surface and a bottom surface; a body region passing through the thickness of the transmission line within the width of the transmission line, wherein the body region includes a first source/drain region and a second source/drain region separated by a channel region, and A gate dielectric surrounding the body region and laterally separating the body region and the transmission line, wherein a thickness of the gate dielectric varies, wherein a thicker region is adjacent to the top surface and the bottom surface.
2. 2. The semiconductor memory device according to claim 1, wherein the first and second source/drain regions are N-type doped and the channel region is P-type doped.
3. 3. The semiconductor memory device according to claim 1, wherein the first and second source/drain regions are P-type doped and the channel region is N-type doped.
4. 4. The semiconductor memory device according to claim 1, wherein the gate dielectric comprises an oxide material.
5. 5. The semiconductor memory device of claim 1, wherein memory cells of the semiconductor memory device comprise 4F 2 form factor memory cells.
6. 6. The semiconductor memory device according to claim 1, further comprising a storage capacitor coupled to the second source/drain region.
7. 7. The semiconductor memory device according to claim 1, wherein the first source/drain region and the second source/drain region are positioned at least partially within the thickness of the transmission line.
8. 8. The semiconductor memory device according to claim 1, wherein the transmission line includes a word line.
9. 9. A semiconductor memory device, comprising: a transmission line having a width and a thickness between a top surface and a bottom surface; A body region passing through the thickness of the transmission line within the width of the transmission line, wherein the body region includes a first source/drain region and a second source/drain region separated by a channel region; A gate oxide surrounding the body region and laterally separating the body region and the transmission line, wherein the gate oxide has a thickness that varies, wherein a thicker region is adjacent to the top surface and the bottom surface, an An oxide promoting dopant within the gate oxide.
10. 10. The semiconductor memory device according to claim 9, wherein the oxide promoting dopant comprises fluorine.
11. 11. The semiconductor memory device according to claim 9, wherein the oxide promoting dopant comprises argon.
12. 12. The semiconductor memory device according to claim 9, wherein the oxide promoting dopant comprises deuterium.
13. 13. The semiconductor memory device according to claim 9, wherein the gate oxide comprises silicon oxide.
14. 14. The semiconductor memory device according to claim 9, wherein the gate oxide comprises a transition metal oxide.
15. 15. A method of forming a semiconductor device, comprising: forming a transistor body region on a semiconductor substrate; Forming a transmission line around the transistor body region; Doping with a dielectric-promoting dopant within regions adjacent opposite ends of the transistor body region, wherein a concentration of the dopant adjacent the opposite ends is higher than in the middle of the transistor body region; Forming a gate dielectric surrounding the transistor body region, wherein: the central portion of the gate dielectric includes a first thickness, and The end of the gate dielectric includes a second thickness that is greater than the first thickness.
16. 16. The method of claim 15, wherein doping with a dielectric enhancing dopant comprises ion implantation of the dielectric enhancing dopant.
17. 17. The method of claim 15, wherein doping with a dielectric-promoting dopant comprises depositing a doping material.
18. 18. The method of claim 15, wherein forming the transmission line includes forming a transmission line including polysilicon.
19. 19. The method of claim 18, wherein forming the transmission line includes forming a plurality of layers, wherein a top transmission line layer and a bottom transmission line layer are doped.
20. 20. The method of claim 19, wherein the transmission line is formed prior to the transistor body region, and wherein forming the gate dielectric includes oxidizing within an opening in the transmission line and then filling the opening with the transistor body region.

Description

Transistor device with selective thick gate dielectric and method Technical Field The present disclosure relates to semiconductor devices and methods of forming the same, and in particular, to transistor devices having selectively thick gate dielectrics. Background A memory device is a semiconductor circuit that provides electronic storage of data for a host system, such as a computer or other electronic device. The memory device may be volatile or nonvolatile. Volatile memory requires power to maintain data and includes devices such as Random Access Memory (RAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), or Synchronous Dynamic Random Access Memory (SDRAM). Nonvolatile memory can retain stored data when unpowered and include devices such as flash memory, read Only Memory (ROM), electrically Erasable Programmable ROM (EEPROM), erasable Programmable ROM (EPROM), resistance variable memory (e.g., phase Change Random Access Memory (PCRAM), resistive Random Access Memory (RRAM), or Magnetoresistive Random Access Memory (MRAM)), and the like. A host system typically includes a host processor, a first amount of main memory (e.g., typically volatile memory, such as DRAM) for supporting the host processor, and one or more storage systems (e.g., typically non-volatile memory, such as flash memory) that provide additional storage to maintain data in addition to or independent of the main memory. A storage system, such as a Solid State Disk (SSD), may include a memory controller and one or more memory devices, including a number of dies or Logical Units (LUNs). In a particular example, each die may include a number of memory arrays and peripheral circuitry thereon, such as die logic or a die processor. The memory controller may include interface circuitry configured to communicate with a host device (e.g., a host processor or interface circuitry) through a communication interface (e.g., a bi-directional parallel or serial communication interface). The present description relates generally to transistor structures and fabrication in Complementary Metal Oxide Semiconductor (CMOS) devices. Disclosure of Invention An aspect of the present disclosure relates to a semiconductor memory device comprising a transmission line having a width and a thickness between a top surface and a bottom surface, a body region traversing the thickness of the transmission line within the width of the transmission line, wherein the body region includes first and second source/drain regions separated by a channel region, and a gate dielectric surrounding the body region and laterally separating the body region and the transmission line, wherein the thickness of the gate dielectric varies, wherein a thicker region is adjacent to the top surface and the bottom surface. Another aspect of the present application relates to a semiconductor memory device comprising a transmission line having a width and a thickness between a top surface and a bottom surface, a body region traversing the thickness of the transmission line within the width of the transmission line, wherein the body region includes first and second source/drain regions separated by a channel region, a gate oxide surrounding the body region and laterally separating the body region from the transmission line, wherein the thickness of the gate oxide varies, wherein a thicker region is adjacent to the top surface and the bottom surface, and an oxide promoting dopant within the gate oxide. Another aspect of the present disclosure relates to a method of forming a semiconductor device comprising forming a transistor body region on a semiconductor substrate, forming a transmission line around the transistor body region, doping with a dielectric-promoting dopant within a region adjacent to opposite ends of the transistor body region, wherein a concentration of the dopant adjacent to the opposite ends is higher than in the middle of the transistor body region, forming a gate dielectric surrounding the transistor body region, wherein a central portion of the gate dielectric comprises a first thickness, and an end of the gate dielectric comprises a second thickness that is greater than the first thickness. Drawings In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. The same numbers with different letter suffixes may represent different instances of similar components. The drawings illustrate, by way of example and not by way of limitation, the various embodiments discussed in this document. FIG. 1 illustrates a memory device according to some example embodiments. FIG. 2A illustrates a top view of a portion of a memory device according to some example embodiments. Fig. 2B illustrates an isometric view of a portion from fig. 2A, according to some example embodiments. FIG. 3 illustrates a cross-sectional view of a portion of a memory device according to some example embodiments. FIG. 4A illustrates