CN-122002802-A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Abstract

A semiconductor device includes a substrate, bit lines on the substrate and extending in a first direction, word lines extending in a second direction, first and second active patterns between the word lines and spaced apart in the first direction, cell capacitors on the first and second active patterns, and shield gates at a level between the word lines and the cell capacitors. Each of the first and second active patterns includes a first dopant region connected to the bit line, a second dopant region connected to the cell capacitor, and a channel region between the first and second dopant regions. The shield gate overlaps the second dopant region of at least one of the first active pattern and the second active pattern in the first direction.

Inventors

• ZHENG WENYONG
• LI XIANGHAO
• Cui Caixuan

Assignees

• 三星电子株式会社

Dates

Publication Date

20260508

Application Date

20251105

Priority Date

20241106

Claims (20)

1. 1. A semiconductor device, comprising: A substrate; a bit line on the substrate and extending in a first direction; A plurality of word lines extending in a second direction intersecting the first direction; first and second active patterns located between the plurality of word lines and spaced apart in the first direction; A unit capacitor on the first and second active patterns, and A plurality of shield gates located at a level between the plurality of word lines and the cell capacitor, Wherein each of the first active pattern and the second active pattern includes the following: a first dopant region connected to the bit line; A second dopant region connected to the cell capacitor, and A channel region between the first and second dopant regions, an The plurality of shield gates overlap the second dopant region of at least one of the first active pattern and the second active pattern in the first direction.
2. 2. The semiconductor device according to claim 1, wherein: the plurality of shield gates overlap the plurality of word lines in a vertical direction intersecting the first direction and the second direction.
3. 3. The semiconductor device according to claim 1, further comprising: and a back gate electrode located between the first active pattern and the second active pattern and extending in the second direction.
4. 4. The semiconductor device according to claim 3, wherein: The plurality of shield gates includes the following: a first shield gate electrode overlapping the back gate electrode in a vertical direction intersecting the first direction and the second direction, and And a second shielding gate overlapping the plurality of word lines in the vertical direction.
5. 5. The semiconductor device according to claim 4, wherein: The back gate electrode and the first shield gate are configured to be applied with different voltages, an The plurality of word lines and the second shield gate are configured to be applied with different voltages.
6. 6. The semiconductor device according to claim 4, wherein: the back gate electrode and the first shield gate are configured to be applied with the same voltage, The plurality of word lines and the second shield gate are configured to be applied with the same voltage, The first shield gate has a work function different from that of the back gate electrode, and The second shield gate has a work function different from that of the plurality of word lines.
7. 7. The semiconductor device according to claim 1, further comprising: an insulating isolation pattern between the first active pattern and the second active pattern, Wherein the plurality of shield gates comprises the following: A first shielding gate overlapping the isolation insulating pattern in a vertical direction intersecting the first direction and the second direction, and And a second shielding gate overlapping the plurality of word lines in the vertical direction.
8. 8. A semiconductor device, comprising: a substrate including a cell array region and a peripheral circuit region; Bit lines located on the cell array region and extending in a first direction; A plurality of word lines extending in a second direction intersecting the first direction; First and second active patterns located on the plurality of word lines and spaced apart in the first direction; A back gate electrode located between the first active pattern and the second active pattern and extending in the second direction; A unit capacitor on the first and second active patterns, and A plurality of shield gates overlapping at least one of the plurality of word lines and the back gate electrode in a vertical direction intersecting the first direction and the second direction, Wherein each of the first active pattern and the second active pattern includes the following: a first dopant region connected to the bit line; A second dopant region connected to the cell capacitor, and A channel region between the first and second dopant regions, an The plurality of shield gates overlap the second dopant region of at least one of the first active pattern and the second active pattern in the first direction.
9. 9. The semiconductor device according to claim 8, wherein: The plurality of shield gates includes the following: a first shielding gate electrode overlapping the back gate electrode in the vertical direction, and And a second shielding gate overlapping the plurality of word lines in the vertical direction.
10. 10. The semiconductor device according to claim 9, wherein: the width of the first shielding grid electrode is different from the width of the second shielding grid electrode.
11. 11. The semiconductor device according to claim 9, wherein: The second shield gate has a width smaller than a width of each of the plurality of word lines.
12. 12. The semiconductor device according to claim 11, wherein: The width of the first shielding grid electrode is smaller than that of the back grid electrode.
13. 13. The semiconductor device according to claim 9, wherein: the plurality of word lines includes a first word line and a second word line adjacent to each other, an The second shield gate overlaps the first word line and the second word line in the vertical direction.
14. 14. The semiconductor device according to claim 9, wherein: the upper surface of the first shielding grid electrode and the upper surface of the second shielding grid electrode are positioned at different horizontal heights.
15. 15. The semiconductor device according to claim 9, wherein: The thickness of the first shielding grid electrode is different from the thickness of the second shielding grid electrode.
16. 16. The semiconductor device according to claim 9, wherein: in the peripheral circuit region, the ends of the first shield gate and the back gate electrode are aligned at substantially the same boundary, and The semiconductor device further includes: A contact wiring line located in the peripheral circuit region; a first contact via connected to the contact wiring line and the back gate electrode, and And a second contact via connected to the contact wiring line and the first shield gate and passing through the back gate electrode.
17. 17. The semiconductor device according to claim 9, wherein: in the peripheral circuit region, the second shield gate and the plurality of word lines extend at different lengths to have a stepped structure, and The semiconductor device further includes: a word line contact located in the peripheral circuit region and connected to the plurality of word lines, and A second shield gate contact located in the peripheral circuit region and connected to the second shield gate on a side further outside than ends of the plurality of word lines.
18. 18. A semiconductor device, comprising: a substrate including a cell array region and a peripheral circuit region; a peripheral circuit structure including a peripheral circuit on the substrate and a peripheral circuit wiring line connected to the peripheral circuit, and A unit structure overlapping with the peripheral circuit structure in a vertical direction, Wherein the unit structure comprises the following: a bit line on the substrate and extending in a first direction intersecting the vertical direction; a plurality of word lines extending in a second direction intersecting the first direction and the vertical direction; a plurality of active patterns located between the plurality of word lines and spaced apart in the first direction; a back gate electrode located between the plurality of active patterns and extending in the second direction; a cell capacitor on the plurality of active patterns; a first shielding gate electrode overlapping the back gate electrode in the vertical direction, and A second shield gate overlapping the plurality of word lines in the vertical direction, Each of the plurality of active patterns includes the following: a first dopant region connected to the bit line; A second dopant region connected to the cell capacitor, and A channel region between the first and second dopant regions, an Each of the first and second shield gates overlaps the second dopant region in the first direction.
19. 19. The semiconductor device according to claim 18, wherein: the peripheral circuit structure further includes a first bond pad and a first bond insulating layer surrounding the first bond pad, The cell structure further includes a second bond pad and a second bond insulating layer surrounding the second bond pad, an The first bonding pad is in contact with the second bonding pad, and the first bonding insulating layer is in contact with the second bonding insulating layer.
20. 20. The semiconductor device according to claim 18, wherein: the cell structure further includes a memory cell and a cell connection wiring line connected to the memory cell, an The semiconductor device further includes a via connecting the peripheral circuit wiring line and the cell connection wiring line.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips Cross Reference to Related Applications The present application claims priority and benefit from korean patent application No. 10-2024-0156558 filed in the korean intellectual property office on month 11 and 6 of 2024, the entire contents of which are incorporated herein by reference. Technical Field The present disclosure relates to a semiconductor device. Background There is a need for techniques to increase the degree of integration of semiconductor devices. In the case of a two-dimensional semiconductor device, the degree of integration is mainly determined by the area occupied by the unit memory cell, and in this regard may depend on the level of micropatterning technology. Incidentally, the micropatterning technique requires expensive equipment. Therefore, although the integration of the two-dimensional semiconductor device is increasing, it is still limited. Thus, a three-dimensional memory device having memory cells arranged in three dimensions is proposed. As components included in a semiconductor memory device become more integrated and miniaturized, it is important to minimize an influence between components included in the semiconductor device to improve the operation performance of the semiconductor device. Disclosure of Invention The present disclosure seeks to provide a semiconductor device having improved reliability and productivity. The semiconductor device according to an embodiment includes a substrate, a bit line on the substrate and extending in a first direction, a plurality of word lines extending in a second direction intersecting the first direction, first and second active patterns between the plurality of word lines and spaced apart in the first direction, a cell capacitor on the first and second active patterns, and a plurality of shield gates at a level between the plurality of word lines and the cell capacitor, each of the first and second active patterns including a first dopant region connected to the bit line, a second dopant region connected to the cell capacitor, and a channel region between the first and second dopant regions, the plurality of shield gates overlapping at least one of the first and second active patterns in the first direction. The semiconductor device according to an embodiment includes a substrate including a cell array region and a peripheral circuit region, a bit line located on the cell array region and extending in a first direction, a plurality of word lines extending in a second direction intersecting the first direction, first and second active patterns located on the plurality of word lines and spaced apart in the first direction, a back gate electrode located between the first and second active patterns and extending in the second direction, a cell capacitor located on the first and second active patterns, a plurality of shield gates overlapping at least one of the plurality of word lines and the back gate electrode in a vertical direction intersecting the first and second directions, each of the first and second active patterns including a first dopant region connected to the bit line, a second dopant region connected to the cell capacitor, and a channel region located between the first and second dopant regions, and the plurality of shield gates overlapping at least one of the first and second active patterns in the first direction. The semiconductor device according to an embodiment includes a substrate including a cell array region and a peripheral circuit region, a peripheral circuit structure including a peripheral circuit on the substrate and a peripheral circuit wiring line connected to the peripheral circuit, and a cell structure overlapping the peripheral circuit structure in a vertical direction, and the cell structure includes a bit line on the substrate and extending in a first direction intersecting the vertical direction, a plurality of word lines extending in a second direction intersecting the first direction and the vertical direction, a plurality of active patterns between the plurality of word lines and spaced apart in the first direction, a back gate electrode between the plurality of active patterns and extending in the second direction, a cell capacitor on the plurality of active patterns, a first shield gate overlapping the back gate electrode in the vertical direction, and a second shield gate overlapping the plurality of word lines in the vertical direction, and each of the plurality of active patterns includes a first dopant region connected to the bit line, a second dopant region connected to the cell capacitor, and a first dopant region between the first dopant region and the second dopant region and the first gate electrode and each of the first dopant region overlaps the first gate region in the first direction. According to the embodiment, since the shielding gate is formed such that it is positioned to overlap the doped re