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CN-122002803-A - Electric fuse memory cell and memory array

CN122002803ACN 122002803 ACN122002803 ACN 122002803ACN-122002803-A

Abstract

The invention discloses an electric fuse storage unit and a storage array thereof, wherein a control tube and fuses of the electric fuse storage unit are formed in the same active area, a strip-shaped polysilicon fuse is positioned at one side of an MOS control tube, one end of the strip-shaped polysilicon fuse is in short connection with one end of a drain end heavy doping area of the nearest MOS control tube, the area of the electric fuse storage unit is greatly reduced, storage unit pairs are conveniently formed in a central symmetry mode to directly carry out combination layout to form a storage unit array, the layout area of the storage array can be reduced, and the layout efficiency of the storage array formed by the electric fuse storage unit is obviously improved. In addition, the strip-shaped polysilicon is adopted as the fuse, so that the fuse is easy to manufacture, convenient to control quality, uniform and controllable in electromigration during programming and high in reliability after programming is finished.

Inventors

  • WANG YINXIANG
  • YAN YING

Assignees

  • 上海华力集成电路制造有限公司

Dates

Publication Date
20260508
Application Date
20241107

Claims (10)

  1. 1. An electric fuse memory cell, characterized in that it comprises a control tube (1) composed of MOS transistors and a fuse (2); the control tube and the fuse wire (2) are formed in the same active area; The fuse wire (2) is a strip-shaped polycrystalline silicon fuse wire and is positioned on the A side of the control tube (1), wherein A is left or right; the length direction of the source end heavy doping region (207), the drain end heavy doping region (208) and the fuse wire (2) of each MOS transistor of the control tube (1) is the front-back direction; the front end and the rear end of the source end heavy doping region (207) and the drain end heavy doping region (208) of each MOS transistor are respectively aligned; The tops of the source end heavy doping regions (207) of the MOS transistors are short-circuited to source metal formed on the first metal layer through contact holes (205); the top of the drain end heavily doped region (208) of each MOS transistor is short-circuited to drain metal formed on the second metal layer through a contact hole (205); the gate structure (206) of each MOS transistor is shorted to the word line metal formed on the second metal layer through the contact hole (205); one end of the fuse wire (2) is short-circuited to the front end or the rear end of the drain heavy doped region (208) of the MOS transistor forming the most A side of the control tube (1), and the other end of the fuse wire is positioned on the middle A side in the front-rear direction of the drain heavy doped region (208) of the MOS transistor forming the most A side of the control tube (1) and is short-circuited to bit line metal formed on the third metal layer through the contact hole (205).
  2. 2. The electrical fuse memory cell of claim 1 wherein, The front end or the rear end of a drain end heavy doping region (208) of the MOS transistor forming the A-most side of the control tube (1) protrudes to the A-side to form an L shape; The A side of the fuse (2) is aligned with the protruding portion A side of the front end or the rear end of the drain-side heavily doped region (208) of the MOS transistor constituting the A-most side of the control tube (1).
  3. 3. The electrical fuse memory cell of claim 1 wherein, The source end heavy doping region (207) and the drain end heavy doping region (208) of each MOS transistor are formed in the active regions at the left side and the right side of the grid structure (206) in a self-aligned mode; The source heavy doped region (207), the drain heavy doped region (208) and the gate structure (206) of each MOS transistor are also long strips in the front-back direction.
  4. 4. The electrical fuse memory cell of claim 1 wherein, The grid structure (206) comprises a grid dielectric layer and a grid polysilicon layer which are sequentially overlapped; the gate dielectric layer is made of a high dielectric constant material or silicon dioxide.
  5. 5. The electrical fuse memory cell of claim 1 wherein, The control tube (1) is formed by connecting N MOS transistors in parallel, wherein N is an integer greater than 1; the gate structures (206) of the MOS transistors are arranged in a longitudinal shape in the front-rear direction; the source (207) or drain (208) heavily doped regions between two gate structures (206) are common to two MOS transistor cells adjacent to each other.
  6. 6. The electrical fuse memory cell of claim 5 wherein, N is 2, 3, 4 or 5.
  7. 7. The electrical fuse memory cell of claim 1 wherein, The MOS transistor is an NMOS transistor.
  8. 8. An electrical fuse memory array formed from electrical fuse memory cells as claimed in any one of claims 1 to 7, characterized by comprising a plurality of memory cell pairs (4); Each memory cell pair (4) includes a left-side electric fuse memory cell (41) and a right-side electric fuse memory cell (42); The fuse (2) of the left electric fuse storage unit (41) is positioned at the left side of the control tube (1), one end of the fuse (2) is short-circuited to the front end of the drain end heavy doping region (208) of the leftmost MOS transistor forming the control tube (1), and the other end of the fuse is positioned at the middle left side in the front-rear direction of the drain end heavy doping region (208) of the leftmost MOS transistor forming the control tube (1); The fuse (2) of the right-side electric fuse storage unit (42) is positioned on the right side of the control tube (1), one end of the fuse (2) is in short circuit with the rear end of the drain-end heavy-doped region (208) of the rightmost MOS transistor forming the control tube (1), and the other end of the fuse is positioned on the right side of the middle part of the drain-end heavy-doped region (208) of the rightmost MOS transistor forming the control tube (1) in the front-rear direction; the fuse (2) of the left-side electric fuse memory cell (41) and the fuse (2) of the right-side electric fuse memory cell (42) are integrally connected in the front-rear direction.
  9. 9. The electrical fuse memory array of claim 8, wherein, The middle connection part of the fuse wire (2) of the left and right electric fuse memory cells in the memory cell pair is short-circuited to the bit line metal formed on the third metal layer through the corresponding contact hole (205); Each gate structure (206) of the left-side electrical fuse memory cell is shorted to a first word line metal formed on the second metal layer through a corresponding contact hole (205); each gate structure (206) of the right-side electrical fuse memory cell is shorted to a second word line metal formed on the second metal layer through a corresponding contact hole (205); the top of the drain end heavily doped region (208) of each MOS transistor of the left electric fuse storage unit is short-circuited to the first drain metal formed on the second metal layer through the contact hole (205); The top of the drain end heavily doped region (208) of each MOS transistor of the right-side electric fuse storage unit is short-circuited to second drain metal formed on the second metal layer through a contact hole (205); the top of the source end heavy doping region (207) of each MOS transistor of the left electric fuse storage unit is short-circuited to a first source metal formed on the first metal layer through a contact hole (205); the top of the source heavy doped region (207) of each MOS transistor of the right-side electric fuse memory cell is shorted to the second source metal formed on the first metal layer through a contact hole (205).
  10. 10. The electrical fuse memory array of claim 9, wherein, The first drain metal is divided into a front end part first drain metal and a rear end part first drain metal on the layout; the second drain metal is divided into a front end part second drain metal and a rear end part second drain metal; the front-end first drain metal is located right above the front end of the drain-end heavily-doped region (208) of the left-side electric fuse memory cell, and the front end of the drain-end heavily-doped region (208) of the left-side electric fuse memory cell is contacted with the front-end first drain metal vertically Kong Duanjie; the rear end part first drain electrode metal is positioned right above the rear end part of the drain end heavy doping region (208) of the left electric fuse memory cell, and the rear end part of the drain end heavy doping region (208) of the left electric fuse memory cell is contacted with the rear end part first drain electrode metal through a vertical contact Kong Duanjie; the front end part second drain electrode metal is positioned right above the front end part of the drain end heavy doping region (208) of the right-side electric fuse storage unit, and the front end part of the drain end heavy doping region (208) of the right-side electric fuse storage unit is contacted with the front end part second drain electrode metal through vertical contact Kong Duanjie; The second drain metal at the rear end part is positioned right above the rear end part of the drain-end heavy-doped region (208) of the right-side electric fuse memory cell, and the second drain metal at the rear end part is contacted with the rear end part of the drain-end heavy-doped region (208) of the right-side electric fuse memory cell through a vertical contact Kong Duanjie; The first source metal is located right above the middle of the drain end heavy doping region (208) of the left electric fuse memory cell, and the first source metal is contacted with the middle of the drain end heavy doping region (208) of the Kong Duanjie electric fuse memory cell vertically; The second source metal is located right above the middle of the drain heavy doping region (208) of the right-side electric fuse memory cell, and the second source metal is contacted with the middle of the drain heavy doping region (208) of the Kong Duanjie right-side electric fuse memory cell vertically; The word line metal is perpendicular to the bit line metal; the word line metal, the drain metal and the source metal are arranged in parallel; The left and right center lines of the front first drain metal and the front second drain metal are positioned on the same straight line and have left and right intervals; the left and right center lines of the rear first drain metal and the rear second drain metal are positioned on the same straight line and have left and right intervals; the vertical projections of the second word line metal, the front-end first drain electrode metal, the first source electrode metal, the rear-end first drain electrode metal and the first word line metal are sequentially arranged in parallel from front to back; the vertical projections of the second word line metal, the front end second drain electrode metal, the second source electrode metal, the rear end second drain electrode metal and the first word line metal are sequentially arranged in parallel from front to back.

Description

Electric fuse memory cell and memory array Technical Field The present invention relates to semiconductor manufacturing technology, and more particularly, to an electronic fuse (efuse) memory cell and a memory array. Background Most eFuse memory cell structures are made up of a fuse and a MOS control tube. It is based on Electromigration (EM) and it implements highly reliable on-chip programming functions by blowing fuses based on the Electromigration (EM) principle. The area size is one of the main design criteria of the efuse memory. In the conventional eFuse memory layout, an eFuse memory cell array area is formed by combining eFuse memory cells, namely, the eFuse memory cell array area is formed by splicing the layout of single eFuse memory cells, the memory cell array area occupies a large part of the whole area of a memory chip, the eFuse memory chip area is mainly determined by an array formed by the eFuse memory cells, wherein the area of a MOS control tube occupies a large part of the whole eFuse memory cell area, and the MOS control tube is a core factor for determining the whole area of the eFuse memory cells. Improving the layout of eFuse memory cells is one of the effective ways to reduce memory chip area. The layout size of an existing efuse memory cell employing a metal fuse is shown in FIG. 1. The efuse memory cell employs a 28nm high dielectric constant (HK) process with an area of 14.4um2, and the efuse cell structure includes a MOS control tube 103 and a fuse 104. The MOS control transistor 103 is typically NMOS and is located in the NMOS region. The fuse 104 is located in the fuse region. In fig. 1, a broken line in a fuse region illustrates a structure of a fuse 104, and the fuse 104 is composed of a PAD (PAD) formed by two metal layers and a metal line connected between the two PADs. When programming, by applying voltage between two PADs, the fusing of the metal wire is realized in an EM mode. In the existing efuse memory cell structure shown in fig. 2, the area of the MOS control tube 103 occupies a large part of the whole memory cell area, and is the main area in the efuse memory cell layout, and the MOS control tube 103 is a core factor for determining the total area of the efuse memory. Disclosure of Invention The invention aims to solve the technical problems of reducing the layout area of a memory array, being easy to manufacture and convenient to control quality, and being uniform and controllable in electromigration during programming and high in reliability after programming is finished. In order to solve the technical problems, the invention provides an electric fuse memory unit, which comprises a control tube 1 formed by MOS transistors and a fuse 2; The control tube 1 and the fuse 2 are formed in the same active area; The fuse 2 is a strip-shaped polycrystalline silicon fuse and is positioned on the A side of the control tube 1, wherein A is left or right; The length direction of the source end heavy doping region 207, the drain end heavy doping region 208 and the fuse 2 of each MOS transistor of the control tube 1 is the front-back direction; The front end and the rear end of the source end heavy doping region 207 and the drain end heavy doping region 208 of each MOS transistor are respectively aligned; the top of the source end heavily doped region 207 of each MOS transistor is shorted to the source metal S formed on the first metal layer M1 through the contact hole 205; the top of the drain heavily doped region 208 of each MOS transistor is shorted to the drain metal D formed on the second metal layer M2 through the contact hole 205; The gate structure 206 of each MOS transistor is shorted to the word line metal W formed on the second metal layer M2 through the contact hole 205; One end of the fuse 2 is short-circuited to the front end or the rear end of the drain heavily doped region 208 of the MOS transistor constituting the most a side of the control tube 1, and the other end is positioned on the middle a side in the front-rear direction of the drain heavily doped region 208 of the MOS transistor constituting the most a side of the control tube 1 and short-circuited to the bit line metal BL formed on the third metal layer M3 through the contact hole 205. Preferably, the front end or the rear end of the drain heavily doped region 208 of the MOS transistor forming the most A side of the control tube 1 protrudes to the A side to form an L shape; the a side of the fuse 2 is aligned with the protruding portion a side of the front or rear end of the drain heavily doped region 208 of the MOS transistor constituting the most a side of the control tube 1. Preferably, the source heavy doped region 207 and the drain heavy doped region 208 of each MOS transistor are formed in the active regions on the left and right sides of the gate structure 206 in a self-aligned manner; the source heavily doped region 207, the drain heavily doped region 208, and the gate structure 206 of each