CN-122002804-A - Semiconductor device and method for manufacturing the same

Abstract

The present application relates to a semiconductor device and a method of manufacturing the semiconductor device. A semiconductor device includes a first stack including first material layers and second material layers alternately stacked, a penetrating structure extending through the first stack and including an air gap, and a second stack located under the first stack and including a key pattern positioned to correspond to the air gap.

Inventors

• JIN ZHONGXUN

Assignees

• 爱思开海力士有限公司

Dates

Publication Date

20260508

Application Date

20250409

Priority Date

20241105

Claims (20)

1. 1. A semiconductor device, the semiconductor device comprising: A first laminate including a first material layer and a second material layer, the first material layer being alternately laminated with the second material layer in a vertical direction; A through structure extending through the first laminate in the vertical direction and including an air gap, and A second stack located below the first stack and including a key pattern positioned to overlap the air gap in the vertical direction.
2. 2. The semiconductor device of claim 1, wherein the through structure comprises: insulating lining element The air gap is located inside the insulating liner.
3. 3. The semiconductor device according to claim 2, further comprising: A metal pattern overlapping the first laminate in the vertical direction, and An interlayer insulating layer between the first laminate and the metal pattern.
4. 4. A semiconductor device according to claim 3, wherein the insulating liner and the interlayer insulating layer are integrally connected single layers.
5. 5. The semiconductor device according to claim 3, further comprising a conductive pattern between the first laminate and the interlayer insulating layer.
6. 6. The semiconductor device according to claim 5, wherein the conductive pattern comprises polysilicon.
7. 7. The semiconductor device of claim 1, wherein the through structure comprises: A metal liner; an insulating liner surrounding the metal liner, and The air gap is located inside the metal liner.
8. 8. The semiconductor device according to claim 7, wherein the metal liner protrudes from an upper surface of the first laminate.
9. 9. The semiconductor device according to claim 1, wherein the second stacked member includes a third material layer and a fourth material layer, wherein the third material layer is alternately stacked with the fourth material layer in the vertical direction, and wherein the second stacked member includes the key pattern on a surface of the second stacked member.
10. 10. The semiconductor device according to claim 9, wherein the third material layer and the fourth material layer are stacked in a shape in which the third material layer and the fourth material layer are recessed toward the through structure, and wherein the key pattern includes a groove in a recessed region.
11. 11. The semiconductor device of claim 1, wherein a width at an upper portion of the through structure is smaller than a width at a lower portion of the through structure.
12. 12. The semiconductor device of claim 1, wherein the through structure is located in a scribe line region.
13. 13. The semiconductor device according to claim 1, further comprising: a memory cell array including a gate structure at a height corresponding to the first stack and the second stack; Peripheral circuit, and And a bonding structure electrically connecting the memory cell array to the peripheral circuit.
14. 14. The semiconductor device according to claim 1, further comprising: a gate structure located at a height corresponding to the first stack and the second stack; A source layer overlapping the gate structure in the vertical direction, and And a metal wiring line located above the source layer.
15. 15. The semiconductor device according to claim 14, further comprising a metal pattern located above the first stack and at a height corresponding to the metal wiring line.
16. 16. A semiconductor device, the semiconductor device comprising: A laminate located in the scribe line region and including a first material layer and a second material layer, the first material layer being alternately laminated with the second material layer in a vertical direction; a metal liner extending through the stack in the vertical direction; An insulating liner surrounding the metal liner; an air gap inside the metal liner, and An interlayer insulating layer overlapping the laminate in the vertical direction.
17. 17. The semiconductor device according to claim 16, further comprising a conductive pattern between the laminate and the interlayer insulating layer.
18. 18. The semiconductor device according to claim 16, further comprising a metal pattern overlapping the interlayer insulating layer in the vertical direction and in contact with the air gap or the metal liner.
19. 19. The semiconductor device according to claim 16, wherein the insulating liner and the interlayer insulating layer are a single layer integrally connected.
20. 20. A method of manufacturing a semiconductor device, the method comprising the steps of: forming a first laminate on a substrate; forming a first opening extending through the first stack into the substrate; forming a sacrificial layer in the first opening; Forming a second laminate over the first laminate; Etching the substrate such that the sacrificial layer is exposed; Forming a second opening by removing the sacrificial layer, and An air gap is formed in the second opening.

Description

Semiconductor device and method for manufacturing the same Technical Field Embodiments of the present disclosure relate to electronic devices, and more particularly, to semiconductor devices and methods of manufacturing semiconductor devices. Background The degree of integration of a semiconductor device is mainly determined by the area occupied by a unit memory cell. Recently, as the improvement of the integration level of a semiconductor device in which memory cells are formed in a single layer on a substrate reaches a limit, a three-dimensional semiconductor device in which memory cells are stacked on a substrate has been proposed. In addition, various structures and manufacturing methods have been developed in order to improve the operational reliability of such semiconductor devices. Disclosure of Invention In an embodiment, a semiconductor device may include a first stack including first material layers and second material layers alternately stacked in a vertical direction, a penetrating structure extending through the first stack in the vertical direction and including an air gap, and a second stack under the first stack and including a key pattern positioned to overlap the air gap in the vertical direction. In an embodiment, a semiconductor device may include a stack located in a scribe line region and including first material layers and second material layers alternately stacked in a vertical direction, a metal liner extending through the stack in the vertical direction, an insulating liner (liner) surrounding the metal liner, an air gap located inside the metal liner, and an interlayer insulating layer overlapping the stack in the vertical direction. In an embodiment, a method of manufacturing a semiconductor device may include forming a first stack on a substrate, forming a first opening extending into the substrate through the first stack, forming a sacrificial layer in the first opening, forming a second stack on the first stack, etching the substrate such that the sacrificial layer is exposed, forming a second opening by removing the sacrificial layer, and forming an air gap in the second opening. In an embodiment, a method of manufacturing a semiconductor device may include forming a stack, forming a contact plug through the stack, forming an opening extending through the stack, forming an insulating layer inside the opening and over the stack, forming a hard mask layer on the insulating layer to include a overhang structure in the opening, forming a mask pattern on the hard mask layer, forming a contact hole by etching the insulating layer using the mask pattern as an etch stop, the contact hole exposing the contact plug, forming a via hole in the contact hole, and forming a metal liner in the opening, the metal liner including an air gap. Drawings Fig. 1A, 1B, 1C, 1D, and 1E are diagrams illustrating a structure of a semiconductor device according to an embodiment. Fig. 2A and 2B are diagrams illustrating a structure of a semiconductor device according to an embodiment. Fig. 3A and 3B are diagrams illustrating a structure of a semiconductor device according to an embodiment. Fig. 4A, 4B, 4C, 4D, and 4E are diagrams for describing a manufacturing method of a semiconductor device according to an embodiment. Fig. 5A, 5B, and 5C are diagrams for describing a manufacturing method of a semiconductor device according to an embodiment. Fig. 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, and 17A and fig. 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, and 17B are diagrams for describing a method of manufacturing a semiconductor device according to an embodiment. Fig. 18 is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure. Fig. 19 is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure. Detailed Description Various embodiments are directed to a semiconductor device having a stable structure and improved characteristics, and a method of manufacturing the semiconductor device. In the embodiment, the integration level of the semiconductor device can be improved by stacking the memory cells in three dimensions. In an embodiment, a semiconductor device having a stable structure and improved reliability may also be provided. Hereinafter, embodiments of the technical concept according to the present disclosure will be described with reference to the accompanying drawings. Terms such as "first," "second," and the like, are used for distinguishing between various elements and not necessarily for indicating the size, order, priority, quantity, or importance of the elements. For example, in one example, a first element may be named a second element, while in another example, a second element may be named a first element. Terms such as "top," "above," "upper," "side," "upper," "lower," "row," "column," "interior," "exterior," and other terms implying relative spatial relationships or orientations are us