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CN-122002805-A - Manufacturing method of SONOS memory with metal grid 1.5T structure

CN122002805ACN 122002805 ACN122002805 ACN 122002805ACN-122002805-A

Abstract

The invention discloses a manufacturing method of a SONOS memory with a metal grid 1.5T structure, wherein a selection tube and a storage tube adopt the same storage unit grid polysilicon layer, when pseudo polysilicon is removed, firstly, a storage unit grid layer stack with a storage tube grid region removed is formed through a photomask, a storage unit grid layer stack with the storage tube grid region reserved is reserved, a semiconductor substrate under the storage tube grid region is exposed to form a storage tube grid structure groove, then an ONO layer is deposited, the ONO layer covers the bottom and the side wall of the storage tube grid structure groove to form the storage tube grid groove, then a first grid metal layer is deposited on the ONO layer, and chemical mechanical grinding is carried out to form the storage tube metal grid. The invention can form the SONOS memory with a smaller metal grid electrode 1.5T structure, and the required photomask is less.

Inventors

  • TANG XIAOLIANG

Assignees

  • 上海华力集成电路制造有限公司

Dates

Publication Date
20260508
Application Date
20241107

Claims (12)

  1. 1. The manufacturing method of the SONOS memory with the metal grid electrode 1.5T structure is characterized by comprising the following steps of; S1, providing a semiconductor substrate (100), wherein the semiconductor substrate (100) is formed with logic device active areas (102) and SONOS memory cell active areas (103) which are separated by shallow trench isolation (110); s2, forming a gate oxide layer (130) on a semiconductor substrate; S3, depositing a grid polycrystalline silicon layer (140) on the grid oxide layer (130); S4, photoetching, wherein a storage unit grid region is defined in the SONOS storage unit active region (103), and a logic device grid region is defined in the logic device active region (102); Etching is stopped on a semiconductor substrate (100) and shallow trench isolation (110), a grid polycrystalline silicon layer (140) and a grid oxide layer (130) outside a storage unit grid region and a logic device grid region are removed, a storage unit grid lamination is formed on the semiconductor substrate (100) of the storage unit grid region, and a logic device grid lamination is formed on the semiconductor substrate (100) of the logic device grid region, wherein the storage unit grid lamination is a storage unit grid oxide layer (131) and a storage unit grid polycrystalline silicon layer (141) which are sequentially overlapped from bottom to top, and the logic device grid lamination is a logic device grid oxide layer (132) and a logic device grid polycrystalline silicon layer (142) which are sequentially overlapped from bottom to top; s5, forming an interlayer dielectric layer (120) covering the semiconductor substrate (100), and then performing chemical mechanical polishing to expose the upper surfaces of the storage unit grid polycrystalline silicon layer (141) and the logic device grid polycrystalline silicon layer (142); s6, photoetching, wherein a left-right adjacent selection tube gate region and a storage tube gate region are defined in the storage unit gate region; etching, stopping on the semiconductor substrate (100), removing the storage unit gate stack of the storage tube gate region and reserving the storage unit gate stack of the selection tube gate region, exposing the semiconductor substrate (100) below the storage tube gate region, and forming a storage tube gate structure groove (181); S7, depositing an ONO layer (150) on the silicon wafer, and forming a storage tube grid groove (182) by covering the bottom and the side wall of the storage tube grid structure groove (181) with the ONO layer (150), wherein the ONO layer (150) covers the exposed upper surfaces of the storage unit grid polycrystalline silicon layer (141) and the logic device grid polycrystalline silicon layer (142); s8, depositing a first grid metal layer (161) on the ONO layer (150); S9, performing chemical mechanical polishing to remove the first gate metal layer (161) outside the storage tube gate groove (182) and expose the upper surface of the storage unit gate polysilicon (141) and the upper surface of the logic device gate polysilicon (142) of the rest of the selection tube gate stack; S10, removing storage unit grid polycrystalline silicon (141) of a storage unit grid lamination of a selection tube grid region, stopping at a storage unit grid oxide layer (131) to form a selection tube grid groove (183), and removing logic device grid polycrystalline silicon (142), stopping at a logic device grid oxide layer (132) to form a logic device grid groove (184); s11, depositing a second grid metal layer (162); S12, performing chemical mechanical polishing, and removing the second gate metal layer (162) except the selection tube gate groove (183) and the logic device gate groove (184) to form a selection tube metal gate, a logic device metal gate and a storage tube metal gate; S13, performing subsequent processes of the SONOS memory cell and the logic device to finish manufacturing of the SONOS memory with the 1.5T structure.
  2. 2. The method of claim 1, wherein the metal gate 1.5T structure SONOS memory fabrication method, In step S1, a well implantation process is performed on the active region to form a P-well or an N-well.
  3. 3. The method of claim 1, wherein the metal gate 1.5T structure SONOS memory fabrication method, The logic device active region (102) includes a core device active region and an input-output device active region.
  4. 4. The method of claim 1, wherein the metal gate 1.5T structure SONOS memory fabrication method, In step S2, a gate oxide layer (130) is formed using an oxidation process.
  5. 5. The method of claim 1, wherein the metal gate 1.5T structure SONOS memory fabrication method, In step S3, the gate polysilicon layer (140) is formed by a low pressure chemical vapor deposition process.
  6. 6. The method of claim 1, wherein the metal gate 1.5T structure SONOS memory fabrication method, In step S7, an ONO layer (150) is formed by low pressure chemical vapor deposition or atomic layer deposition.
  7. 7. The method of claim 1, wherein the metal gate 1.5T structure SONOS memory fabrication method, The first gate metal layer (161) is AL; The second gate metal layer (162) is AL.
  8. 8. The method of claim 1, wherein the metal gate 1.5T structure SONOS memory fabrication method, In step S4, a memory cell gate stack is formed on the SONOS memory cell active region (103), a logic device gate stack is formed on the logic device active region (102), and then a sidewall 190 is formed on the memory cell gate stack and the lateral periphery of the logic device gate stack.
  9. 9. The method of claim 1, wherein the metal gate 1.5T structure SONOS memory fabrication method, In step S13, an LDD ion implantation process step is performed.
  10. 10. The method of claim 1, wherein the metal gate 1.5T structure SONOS memory fabrication method, In step S13, an annealing process step is performed.
  11. 11. The method of claim 1, wherein the metal gate 1.5T structure SONOS memory fabrication method, In step S4, the gate oxide layer (130) outside the memory cell gate region and the logic device gate region is removed by cleaning with hydrofluoric acid.
  12. 12. The method of claim 1, wherein the metal gate 1.5T structure SONOS memory fabrication method, After step S6, a threshold voltage adjusting ion implantation is performed on the semiconductor substrate (100) under the exposed memory tube gate region, and then step S7 is performed.

Description

Manufacturing method of SONOS memory with metal grid 1.5T structure Technical Field The invention relates to a semiconductor manufacturing technology, in particular to a manufacturing method of a SONOS memory with a metal gate 1.5T structure. Background In a semiconductor integrated circuit, a Flash Memory (Flash Memory) is widely used in consumer electronic products such as a mobile phone and a digital camera and in a portable system due to its Non-Volatile (Non-Volatile) characteristic. The non-volatile memory technology mainly includes floating gate (floating gate) technology, voltage division gate (SPLIT GATE) technology, and SONOS (Silicon-Oxide-Nitride-Oxide-Silicon, silicon-Silicon Oxide-Silicon Nitride-Silicon Oxide-Silicon) technology, and SONOS type flash memory is widely used due to advantages of simple process, low operation voltage, high data reliability, easy integration into standard CMOS process, and the like. The conventional SONOS memory cell is a 2T (transistor) structure, which includes two transistors capable of independent operation, one is a select transistor (SG, SELECT GATE) and the other is a Memory Gate (MG) which uses an ONO (SiO 2-Si3N4-SiO 2) layer as a gate dielectric, and can store charges in Si3N4 therein. The two transistors of the SONOS memory cell with the 1.5T structure are in close contact arrangement, so that the area of the memory cell can be obviously reduced compared with that of the SONOS memory cell with the 2T structure, but two layers of grid polycrystalline silicon are needed, a double-polysilicon deposition (poly dep) process is needed, an additional photomask and a process are added, and the process difficulty is high. As technology nodes advance, logic process has transitioned from 28nm to metal gate process, and 1.5T fabrication process is more complex. The current method for manufacturing the SONOS memory with the 1.5T structure is to deposit the first layer of gate polysilicon, then etch the gate of one of the devices forming the SONOS memory cell, which may be a selection tube or a memory tube, then manufacture the gate dielectric of the other device and the peripheral logic device (such as a core device and an input/output device) of the memory, deposit the second layer of polysilicon, manufacture the peripheral logic device gate of the memory by using the second layer of polysilicon, and form the gate of the other device by using the second layer of polysilicon, thereby completing the manufacture of the SONOS memory with the 1.5T structure. As described above, after completing the first device in the SONOS memory cell of the 1.5T structure, in order to properly form the gate dielectrics of the second device and the peripheral logic device, and to properly form the shape of the second gate electrode during the etching of the second polysilicon gate electrode, additional masks and processes are required, which increases the complexity and cost of the process, and the process of forming the 1.5T SONOS memory cell and the logic device manufacturing process may be mutually affected, thereby affecting the device performance. Disclosure of Invention The invention aims to provide a manufacturing method of a metal gate 1.5T structure SONOS memory, which can form a metal gate 1.5T structure SONOS memory with smaller size and needs less photomask. In order to solve the technical problems, the manufacturing method of the SONOS memory with the metal grid electrode 1.5T structure provided by the invention comprises the following steps of; S1, providing a semiconductor substrate 100, wherein the semiconductor substrate 100 is formed with a logic device active region 102 and a SONOS memory cell active region 103 which are separated by a shallow trench isolation 110; s2, forming a gate oxide layer 130 on the semiconductor substrate; S3, depositing a gate polysilicon layer 140 on the gate oxide layer 130; s4, photoetching, wherein a storage unit gate region is defined in the SONOS storage unit active region 103, and a logic device gate region is defined in the logic device active region 102; Etching is stopped on the semiconductor substrate 100 and the shallow trench isolation 110, the gate polysilicon layer 140 and the gate oxide layer 130 outside the memory cell gate region and the logic device gate region are removed, a memory cell gate stack is formed on the semiconductor substrate 100 of the memory cell gate region, and a logic device gate stack is formed on the semiconductor substrate 100 of the logic device gate region, wherein the memory cell gate stack is a memory cell gate oxide layer 131 and a memory cell gate polysilicon layer 141 which are sequentially overlapped from bottom to top, and the logic device gate stack is a logic device gate oxide layer 132 and a logic device gate polysilicon layer 142 which are sequentially overlapped from bottom to top; S5, forming an interlayer dielectric layer 120 covering the semiconductor substrate 100, and then performing