CN-122002806-A - Semiconductor structure, preparation method thereof, memory and memory system

Abstract

The embodiment of the application provides a semiconductor structure, a preparation method of the semiconductor structure, a memory and a storage system, wherein the semiconductor structure comprises a stacked structure and a connection structure, the stacked structure comprises insulating layers and gate layers which are alternately stacked, the connection structure comprises a conductive layer and a first isolation layer, the conductive layer extends in the stacked structure along a first direction and is connected with a gate layer on one side of the conductive layer along the first direction, and the first isolation layer is positioned between the conductive layer and the stacked structure along a direction intersecting the first direction.

Inventors

• ZHANG ZHONG
• WANG DI
• ZHANG KUN
• ZHOU WENXI

Assignees

• 长江存储科技有限责任公司

Dates

Publication Date

20260508

Application Date

20241101

Claims (20)

1. 1. A semiconductor structure, comprising: A stacked structure including insulating layers and gate layers alternately stacked; a connection structure, comprising: A conductive layer extending in the stacked structure along a first direction and connecting one of the gate layers on one side of the conductive layer along the first direction, and A first isolation layer is located between the conductive layer and the stacked structure in a direction intersecting the first direction.
2. 2. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises: The first support structure is positioned in the stacking structure and positioned on one side of the connecting structure along the first direction.
3. 3. The semiconductor structure of claim 2, wherein one of the connection structures is located on a side of the plurality of first support structures in a direction opposite to the first direction, or one of the connection structures is located on a side of one of the first support structures in a direction opposite to the first direction.
4. 4. The semiconductor structure of claim 2, wherein the material of the first support structure comprises an insulating dielectric material.
5. 5. The semiconductor structure of claim 2, wherein the first support structure is in contact with a portion of the conductive layer.
6. 6. The semiconductor structure of claim 2, wherein the connection structure further comprises: A second isolation layer located between the conductive layer and the first support structure; wherein the second isolation layer has a smaller dimension than an end portion of the conductive layer on one side in the first direction in a direction intersecting the first direction.
7. 7. The semiconductor structure of claim 6, wherein the second isolation layer extends through the gate layer between the first support structure and the conductive layer in the first direction.
8. 8. The semiconductor structure of claim 2, wherein the semiconductor structure further comprises: a semiconductor layer located at one side of the stacked structure along the first direction; Wherein the first support structure also extends into the semiconductor layer.
9. 9. The semiconductor structure of claim 2, wherein a dimension of the first support structure is smaller than a dimension of the conductive layer in a direction intersecting the first direction.
10. 10. The semiconductor structure of claim 1, wherein a distance from a surface of the conductive layer on a side opposite to the first direction to a surface of the stacked structure on a side along the first direction is greater than a distance from a surface of the first isolation layer on a side opposite to the first direction to a surface of the stacked structure on a side along the first direction.
11. 11. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises: An isolation structure located at a side of the connection structure along a second direction and penetrating through the stacked structure along the first direction; Wherein the second direction intersects the first direction.
12. 12. The semiconductor structure of claim 11, wherein a height of a surface of the isolation structure on a side opposite to the first direction in the first direction is between a height of a surface of the first isolation layer on a side opposite to the first direction and a height of a surface of the conductive layer on a side opposite to the first direction with respect to a surface of the stacked structure on a side along the first direction.
13. 13. The semiconductor structure of claim 11, wherein sidewalls of the isolation structure along both sides of the second direction are wavy.
14. 14. The semiconductor structure of claim 11, wherein the semiconductor structure further comprises: and the second supporting structure is positioned between the connecting structure and the isolating structure in the second direction and penetrates through the stacking structure along the first direction.
15. 15. The semiconductor structure of claim 14, wherein the material of the second support structure comprises an insulating dielectric material.
16. 16. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises: A channel structure located at a side of the connection structure along a third direction and penetrating the stacked structure along the first direction; Wherein the third direction intersects the first direction.
17. 17. A method of fabricating a semiconductor structure, comprising: forming a stacked structure; Forming a connecting structure; Wherein the stacked structure includes insulating layers and gate layers alternately stacked; Wherein, the connection structure includes: A conductive layer extending in the stacked structure along a first direction and connected to one of the gate layers on one side of the conductive layer along the first direction, and A first isolation layer is located between the conductive layer and the stacked structure in a direction intersecting the first direction.
18. 18. The method of manufacturing of claim 17, wherein forming the stacked structure comprises: Forming an initial stack structure including insulating layers and sacrificial dielectric layers alternately stacked, and Replacing the sacrificial dielectric layer with the grid electrode layer to form the stacked structure; wherein forming the connection structure comprises: Forming a first opening extending in the first direction in the initial stacked structure; Forming a first isolation layer on the side wall of the first opening; forming a first sacrificial layer in the first opening; Removing the first sacrificial layer in response to replacing the sacrificial dielectric layer with the gate layer, and The conductive layer is formed in the first opening in response to removing the first sacrificial layer.
19. 19. The method of manufacturing of claim 18, wherein forming the first isolation layer on the sidewall of the first opening comprises: Forming an initial isolation layer on the side wall of the first opening and the inner wall of one side of the first opening along the first direction, and And etching a part of the inner wall of the initial isolation layer, which is positioned on one side of the first opening along the first direction, to expose the grid layer, which is positioned on one side of the first opening along the first direction, wherein the part of the initial isolation layer, which is positioned on the side wall of the first opening, forms the first isolation layer.
20. 20. The manufacturing method according to claim 19, wherein etching a portion of the inner wall of the initial isolation layer on the side of the first opening in the first direction comprises: Etching to remove a part of the inner wall of the initial isolation layer, which is positioned at one side of the first opening along the first direction, and forming a second isolation layer by the rest part of the initial isolation layer, which is positioned at one side of the first opening along the first direction; Or etching to remove all the inner walls of the initial isolation layer, which are positioned on one side of the first opening along the first direction.

Description

Semiconductor structure, preparation method thereof, memory and memory system Technical Field The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor structure, a method for manufacturing the semiconductor structure, a memory, and a memory system. Background Memory is one of the important components in electronic systems. Flash memory is an important type of memory. Flash Memory (Flash Memory) is also called Flash Memory, and the main characteristic of Flash Memory is that it can keep stored information for a long time without power-up, and has the advantages of high integration level, fast access speed, easy erasing and rewriting, etc., so it becomes the main stream Memory of non-volatile Memory. Flash Memory is classified into a NOR Flash Memory (NOR Flash Memory) and a nand Flash Memory (NAND FLASH Memory) according to the difference in structure. The NAND FLASH Memory provides a high cell density, can achieve a high Memory density, and also has a faster writing and erasing speed than the NOR Flash Memory. With the tremendous progress in semiconductor manufacturing processes, three-dimensional (3D) flash memory applications, such as 3D nand flash memory, are pursuing lower unit cell manufacturing costs. Disclosure of Invention The present application provides a semiconductor structure, a method of fabricating a semiconductor structure, a memory and a memory system that at least partially address the above-mentioned problems, or other problems in the art. In one aspect, the present application provides a semiconductor structure including a stacked structure including insulating layers and gate layers alternately stacked, and a connection structure including a conductive layer extending in a first direction in the stacked structure and connecting a gate layer on one side of the conductive layer in the first direction, and a first isolation layer located between the conductive layer and the stacked structure in a direction intersecting the first direction. In some embodiments, the semiconductor structure further includes a first support structure located in the stacked structure and on one side of the connection structure in the first direction. In some embodiments, one connection structure is located on one side of the plurality of first support structures in a direction opposite to the first direction, or one connection structure is located on one side of one first support structure in a direction opposite to the first direction. In some embodiments, the material of the first support structure comprises an insulating dielectric material. In some embodiments, the first support structure is in contact with a portion of the conductive layer. In some embodiments, the connection structure further includes a second isolation layer between the conductive layer and the first support structure, wherein a dimension of the second isolation layer in a direction intersecting the first direction is smaller than a dimension of an end of the conductive layer along one side of the first direction. In some embodiments, the second spacer layer extends through the gate layer between the first support structure and the conductive layer in the first direction. In some embodiments, the semiconductor structure further comprises a semiconductor layer located on one side of the stacked structure along the first direction, wherein the first support structure further extends into the semiconductor layer. In some embodiments, the first support structure has a dimension that is smaller than a dimension of the conductive layer in a direction that intersects the first direction. In some embodiments, a distance from a surface of the conductive layer along a side opposite to the first direction to a surface of the stacked structure along the first direction is greater than a distance from a surface of the first isolation layer along a side opposite to the first direction to a surface of the stacked structure along the first direction. In some embodiments, the semiconductor structure further includes an isolation structure located at a side of the connection structure along a second direction and penetrating the stacked structure along a first direction, wherein the second direction intersects the first direction. In some embodiments, the height of the surface of the isolation structure on the side opposite to the first direction is between the height of the surface of the first isolation layer on the side opposite to the first direction and the height of the surface of the conductive layer on the side opposite to the first direction in the first direction with respect to the surface of the stacked structure on the side along the first direction. In some embodiments, the sidewalls of the isolation structure on both sides in the second direction are wavy. In some embodiments, the semiconductor structure further includes a second support structure located between the connection stru