CN-122002807-A - Semiconductor device and data storage system including the same

Abstract

A semiconductor device and a data storage system including the semiconductor device are provided. The semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a circuit element on a first substrate, a lower interconnect structure coupled with the circuit element, and a lower bonding structure coupled with the lower interconnect structure. The second semiconductor structure includes an upper bonding structure bonded to the lower bonding structure, a conductive layer, a stacked structure including an interlayer insulating layer and a gate electrode, a plurality of separation regions at least partially penetrating the stacked structure, a channel structure including a channel layer and at least partially penetrating the stacked structure, a plurality of address pillars spaced apart from each other by a first separation distance, a plurality of channel pillars under the channel structure, and an upper interconnect structure under the stacked structure, coupled with the plurality of channel pillars, and spaced apart from the plurality of address pillars.

Inventors

• Pu Bingkun
• WU XUANXI
• PU JUNFAN
• SHEN YONGJUN
• WU SHOUZHI
• Jin Mengen

Assignees

• 三星电子株式会社

Dates

Publication Date

20260508

Application Date

20250826

Priority Date

20241107

Claims (20)

1. 1. A semiconductor device, comprising: a first semiconductor structure, comprising: A first substrate; A circuit element on the first substrate; A lower interconnect structure coupled to the circuit element, and A lower joint structure coupled with the lower interconnect structure, and A second semiconductor structure, comprising: an upper engagement structure engaged to the lower engagement structure; A conductive layer; a stacked structure below the conductive layer and including an interlayer insulating layer and a gate electrode stacked in a first direction, the first direction being perpendicular to an upper surface of the conductive layer; A plurality of separation regions at least partially penetrating the stacked structure, extending in a second direction perpendicular to the first direction and spaced apart from each other in a third direction perpendicular to the first and second directions; A channel structure comprising a channel layer and penetrating at least partially through the stacked structure in the first direction; a plurality of address pillars spaced apart from each other in the second direction by a first separation distance under at least one of the plurality of separation regions; A plurality of channel pillars under the channel structure, and An upper interconnect structure is coupled with the plurality of channel pillars and spaced apart from the plurality of address pillars below the stack structure.
2. 2. The semiconductor device of claim 1, wherein each address pillar of the plurality of address pillars comprises a first upper surface, a first lower surface, and a first side surface between the first upper surface and the first lower surface, Wherein each channel pillar of the plurality of channel pillars includes a second upper surface, a second lower surface, and a second side surface between the second upper surface and the second lower surface, and Wherein the first lower surfaces of the plurality of address pillars are disposed at the same level as the second lower surfaces of the plurality of channel pillars.
3. 3. The semiconductor device of claim 2, wherein the first upper surfaces of the plurality of address pillars are disposed below a third lower surface of the at least one separation region, Wherein in each address column of the plurality of address columns, the width of the first upper surface is smaller than the width of the first lower surface, and Wherein a width of the third lower surface of the at least one separation region is greater than the width of the first lower surface of each address column of the plurality of address columns.
4. 4. The semiconductor device of claim 3, wherein the third lower surface of the at least one separation region is spaced apart from the first upper surface of each of the plurality of address pillars in the first direction.
5. 5. The semiconductor device according to claim 3, further comprising: A base layer between the third lower surface of the at least one separation region and the first upper surface of each address column of the plurality of address columns.
6. 6. The semiconductor device of claim 2, wherein a first reference line passing through a center of the first upper surface of each address pillar of the plurality of address pillars in the first direction is offset from a second reference line passing through a center of a width of the at least one separation region in the third direction.
7. 7. The semiconductor device according to claim 2, further comprising: an upper insulating layer between the first lower surface of each address pillar of the plurality of address pillars and the upper interconnect structure, Wherein the plurality of address pillars are isolated from the upper interconnect structure by the upper insulating layer.
8. 8. The semiconductor device of claim 1, wherein a first length of each of the plurality of address pillars in the first direction is equal to a second length of each of the plurality of channel pillars in the first direction.
9. 9. The semiconductor device of claim 1, wherein a first length of each of the plurality of address pillars in the first direction is less than a second length of each of the plurality of channel pillars in the first direction.
10. 10. The semiconductor device of claim 1, wherein the upper interconnect structure comprises a bit line coupled with the plurality of channel pillars, extending in the third direction and spaced apart from each other in the second direction, and Wherein the first separation distance is a multiple of a pitch of the bit lines.
11. 11. The semiconductor device of claim 1, further comprising: an upper gate electrode between the channel structure and the plurality of channel pillars; An upper channel structure at least partially penetrating the upper gate electrode and coupled to each of the channel structures, and An insulating region at least partially penetrating the upper gate electrode and disposed under the plurality of separation regions, Wherein the plurality of address posts are disposed below the insulating region.
12. 12. The semiconductor device of claim 11, wherein a first reference line passing through a center of an upper surface of each of the plurality of address pillars in the first direction is coaxial with a second reference line passing through a center of a width of the at least one separation region in the third direction, and is offset from a third reference line passing through a center of a width of the insulation region in the third direction.
13. 13. The semiconductor device of claim 11, wherein a width of an upper surface of each of the plurality of address pillars is smaller than a width of a lower surface of each of the plurality of separation regions.
14. 14. A semiconductor device, comprising: a first semiconductor structure, comprising: A first substrate; A circuit element on the first substrate; A lower interconnect structure coupled to the circuit element, and A lower joint structure coupled with the lower interconnect structure, and A second semiconductor structure, comprising: an upper engagement structure engaged to the lower engagement structure; A conductive layer; a stacked structure below the conductive layer and including an interlayer insulating layer and a gate electrode stacked in a first direction, the first direction being perpendicular to an upper surface of the conductive layer; A channel structure comprising a channel layer and penetrating at least partially through the stacked structure in the first direction; a plurality of separation regions at least partially penetrating the stacked structure, extending in a second direction and spaced apart from each other in a third direction, the second direction being perpendicular to the first direction, the third direction being perpendicular to the first direction and the second direction, the plurality of separation regions including an address separation group including a first address separation region and a second address separation region adjacent to the first address separation region in the third direction; A plurality of address posts spaced apart from each other in the second direction by a multiple of a unit separation distance and disposed under the first address separation region and the second address separation region, and And a plurality of channel pillars disposed below the channel structure.
15. 15. The semiconductor device according to claim 14, wherein the first address separation region is provided one every n separation regions in the third direction, n is a positive integer greater than zero (0), and Wherein the second address separation region includes the remaining separation regions other than the first address separation region among the plurality of separation regions.
16. 16. The semiconductor device of claim 14, wherein the plurality of address pillars comprises at least one address pillar disposed in a location determined based on a same array rule used to set each of the address separation groups.
17. 17. The semiconductor device of claim 14, wherein the plurality of address pillars are disposed in different locations based on different array rules for setting the address separation group.
18. 18. The semiconductor device of claim 14, further comprising: an upper interconnect structure coupled with the plurality of channel pillars and spaced apart from the plurality of address pillars, Wherein the upper interconnect structure includes a bit line coupled with the plurality of channel pillars, extending in the third direction, and spaced apart from each other in the second direction, and Wherein the unit separation distance is a multiple of a pitch of the bit lines.
19. 19. A data storage system, comprising: A semiconductor device, comprising: a first semiconductor structure including a substrate and a circuit element on the substrate; A second semiconductor structure including a stacked structure including an interlayer insulating layer and a gate electrode stacked in a first direction, and a channel structure penetrating at least partially through the stacked structure, and An input/output pad coupled to the circuit element, and A controller coupled to the semiconductor device via the input/output pads and configured to control the semiconductor device, Wherein the first semiconductor structure further comprises: A lower interconnect structure coupled to the circuit element, and A lower engagement structure coupled with the lower interconnect structure, Wherein the second semiconductor structure further comprises: an upper interconnect structure disposed under the stack structure; an upper bonding structure coupled with the upper interconnect structure and bonded to the lower bonding structure; A plurality of separation regions at least partially penetrating the stacked structure and extending in a second direction, the second direction being perpendicular to the first direction, and spaced apart from each other in a third direction, the third direction being perpendicular to the first and second directions; A plurality of address posts disposed under at least one of the plurality of divided regions and spaced apart from each other in the second direction by a first separation distance, and A plurality of channel pillars under the channel structure, and Wherein the upper interconnect structure is coupled with the plurality of channel pillars and spaced apart from the plurality of address pillars.
20. 20. The data storage system of claim 19, wherein the plurality of address pillars are disposed only under a first address separation region among the plurality of separation regions in the second direction, and Wherein the first address separation region is set one every n separation regions in the third direction, n being a positive integer greater than zero (0).

Description

Semiconductor device and data storage system including the same Technical Field The present disclosure relates generally to semiconductor devices, and more particularly, to a semiconductor device and a data storage system including the same. Background Data storage systems that may require data storage may use semiconductor devices capable of storing relatively large amounts of data. Accordingly, methods for potentially increasing the data storage capacity of semiconductor devices have been studied. For example, a possible method for potentially increasing the data storage capacity of a semiconductor device may include arranging the memory cells of the semiconductor device in three dimensions, rather than arranging the memory cells in two dimensions. Disclosure of Invention One or more example embodiments of the present disclosure provide a semiconductor device that has relatively high reliability and is capable of performing quality inspection when compared to related semiconductor devices. Accordingly, a highly reliable semiconductor device and a data storage system including the same can be provided by error checking with improved reliability. Further, one or more example embodiments of the present disclosure provide a data storage system including a semiconductor device having relatively high reliability and capable of performing an error checking operation. According to one aspect of the present disclosure, a semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate, a circuit element on the first substrate, a lower interconnect structure coupled with the circuit element, and a lower bonding structure coupled with the lower interconnect structure. The second semiconductor structure includes an upper bonding structure bonded to the lower bonding structure, a conductive layer, a stack structure under the conductive layer and including an interlayer insulating layer and a gate electrode stacked in a first direction, a plurality of separation regions extending at least partially through the stack structure and spaced apart from each other in a second direction, a channel structure including the channel layer and at least partially through the stack structure in the first direction, a plurality of address pillars spaced apart from each other in the second direction by a first separation distance under at least one of the plurality of separation regions, a plurality of channel pillars under the channel structure, and an upper interconnect structure under the stack structure coupled with the plurality of channel pillars and spaced apart from the plurality of address pillars. The first direction is perpendicular to the upper surface of the conductive layer. The second direction is perpendicular to the first direction. The third direction is perpendicular to the first direction and the second direction. According to one aspect of the present disclosure, a semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate, a circuit element on the first substrate, a lower interconnect structure coupled with the circuit element, and a lower bonding structure coupled with the lower interconnect structure. The second semiconductor structure includes an upper bonding structure bonded to the lower bonding structure, a conductive layer, a stack structure under the conductive layer and including an interlayer insulating layer and a gate electrode stacked in a first direction, a channel structure including a channel layer and penetrating the stack structure at least partially in the first direction, a plurality of separation regions extending at least partially through the stack structure in a second direction and spaced apart from each other in a third direction, a plurality of address pillars spaced apart from each other in the second direction by a multiple of a unit separation distance and disposed under the first address separation region and the second address separation region, and a plurality of channel pillars disposed under the channel structure. The first direction is perpendicular to the upper surface of the conductive layer. The second direction is perpendicular to the first direction. The third direction is perpendicular to the first direction and the second direction. The plurality of divided regions includes an address dividing group including a first address dividing region and a second address dividing region adjacent to the first address dividing region in a third direction. According to one aspect of the disclosure, a data storage system includes a semiconductor device and a controller coupled to the semiconductor device via input/output pads and configured to control the semiconductor device. The semiconductor device includes a first semiconductor structure including a substrate and a circuit element on th