CN-122002808-A - Semiconductor structure, preparation method thereof and storage system

Abstract

The disclosure provides a semiconductor structure, a preparation method thereof and a storage system, relates to the technical field of semiconductor chips, and aims to solve the problem that a conductive structure for testing occupies a large space. The semiconductor structure includes a channel structure, a plurality of support pillars, a first conductive structure, and a second conductive structure. The trench structure extends along a first direction, the plurality of support columns are arranged around the trench structure, the support columns extend along the first direction, the first conductive structure is located on a first side of the trench structure along a second direction, the second direction crosses the first direction, the second conductive structure is located on the first side, and at least one support column is arranged between the first conductive structure and the second conductive structure. Through the arrangement, the first conductive structure and the second conductive structure can occupy no extra space, so that the size of the semiconductor structure in the second direction and the third direction is reduced, and the semiconductor structure is further miniaturized.

Inventors

• JIA CAIYAN
• CHEN LIANG
• LIU WEI
• HUANG LEI

Assignees

• 长江存储科技有限责任公司

Dates

Publication Date

20260508

Application Date

20241108

Claims (20)

1. 1. A semiconductor structure, comprising: a channel structure extending in a first direction; A plurality of support columns disposed about the channel structure, the support columns extending in the first direction; the first conductive structure is positioned on a first side of the channel structure along a second direction, and the second direction is intersected with the first direction; The second conductive structure is positioned on the first side, and at least one supporting column is arranged between the first conductive structure and the second conductive structure.
2. 2. The semiconductor structure of claim 1, wherein the first conductive structure comprises: a conductive portion including a conductive pillar and an insulating layer, the conductive pillar and the insulating layer each extending in the first direction, and the insulating layer being disposed around the conductive pillar; the conductive block is positioned on one side of the conductive part along the first direction, extends along the second direction and the third direction, is connected with the conductive column, and is intersected with the plane in which the first direction and the second direction are positioned.
3. 3. The semiconductor structure of claim 2, wherein, The conductive portions and the plurality of support columns are arranged along a second direction, and the conductive portions and the plurality of support columns are arranged along a third direction.
4. 4. The semiconductor structure of claim 3, wherein the conductive portion has a dimension in the second direction that is the same as a dimension of the support column in the second direction on the reference plane, and/or On the reference surface, the dimension of the conductive part in the third direction is the same as the dimension of the support column in the third direction; The reference plane intersects the first direction.
5. 5. The semiconductor structure of claim 2, wherein the first conductive structure comprises a plurality of conductive portions, the plurality of conductive portions being connected to the same conductive block.
6. 6. The semiconductor structure of claim 5, wherein in the second direction, the support columns adjacent to the conductive portion are first sub-columns, a spacing between the first sub-columns and the conductive portion is a first distance, and a spacing between two adjacent support columns is equal to the first distance.
7. 7. The semiconductor structure of claim 5, wherein in the third direction, the support columns adjacent to the conductive portion are second sub-columns, a spacing between the second sub-columns and the conductive portion is a second distance, and a spacing between two adjacent support columns is equal to the second distance.
8. 8. The semiconductor structure of claim 5, wherein a spacing between adjacent two of the support pillars in the second direction is equal to a spacing between adjacent two of the conductive portions.
9. 9. The semiconductor structure of claim 5, wherein a spacing between adjacent two of the support pillars is equal to a spacing between adjacent two of the conductive portions in the third direction.
10. 10. The semiconductor structure of claim 2, wherein in the second direction any of the support posts is located between the conductive portion and the channel structure, or in the third direction any of the support posts is located between the conductive portion and the channel structure.
11. 11. The semiconductor structure of claim 2, wherein in the first direction, the conductive block covers at least one support pillar.
12. 12. The semiconductor structure of claim 2, wherein a dimension of the conductive portion in the second direction and a dimension of the conductive portion in the third direction are both less than 150nm.
13. 13. The semiconductor structure of claim 2, wherein the semiconductor structure comprises a plurality of the first conductive structures, the plurality of first conductive structures being spaced apart; the minimum distance between adjacent conductive bumps is greater than 3 μm.
14. 14. The semiconductor structure of claim 1, further comprising a first gate isolation structure and a second gate isolation structure, the first gate isolation structure extending in a second direction, the second gate isolation structure extending in the second direction, the first gate isolation structure and the second gate isolation structure being spaced apart along a third direction, the first gate isolation structure and the second gate isolation structure being located between the channel structure and the support post, the second direction intersecting the third direction, a plane in which the second direction and the third direction lie intersecting the first direction; the first conductive structure is located between the first gate isolation structure and the second gate isolation structure.
15. 15. The semiconductor structure of any one of claims 1-14, wherein, The semiconductor structure includes: a first stacked structure including gate layers and first dielectric layers alternately stacked in the first direction; a second stacked structure adjacent to the first stacked structure in a second direction and a third direction, the second stacked structure including second dielectric layers and third dielectric layers alternately stacked in the first direction; the second direction intersects with the third direction, and a plane where the second direction and the third direction are located intersects with the first direction; the channel structure penetrates through the first stacking structure; at least a portion of the support posts extend through the second stacked structure.
16. 16. The semiconductor structure of claim 15, wherein the channel structure comprises a channel layer and a memory functional layer, the memory functional layer being located between the channel layer and the first stack structure.
17. 17. The semiconductor structure of claim 15, wherein the support posts comprise an insulating material.
18. 18. The semiconductor structure of claim 15, wherein the semiconductor structure comprises a plurality of first conductive structures extending through the second stacked structure.
19. 19. The semiconductor structure of claim 15, wherein the semiconductor structure comprises a plurality of first conductive structures, a portion of the first conductive structures extending through the first stack structure, and a portion of the first conductive structures extending through the second stack structure.
20. 20. The semiconductor structure of claim 15, further comprising a first connection structure extending through a portion of the first stack structure, and wherein the first connection structure is connected to the gate layer.

Description

Semiconductor structure, preparation method thereof and storage system Technical Field The disclosure relates to the technical field of semiconductor chips, and in particular relates to a semiconductor structure, a preparation method thereof and a storage system. Background To achieve high integration and miniaturization of memory, three-dimensional (3D) memories have been developed. In 3D NAND memories, array transistors forming vertical memory cell strings and peripheral transistors forming peripheral circuits are typically included. In a 3D NAND device, external circuitry may provide control signals to transistors in a three-dimensional memory via pad-out structures of the memory to enable control of the memory. Disclosure of Invention Embodiments of the present disclosure provide a semiconductor structure, a method of manufacturing the same, and a memory system. The embodiment of the disclosure adopts the following technical scheme: In one aspect, some embodiments of the present disclosure provide a semiconductor structure including a channel structure, a plurality of support pillars, a first conductive structure, and a second conductive structure. The channel structure extends along a first direction, a plurality of support columns are arranged around the channel structure, the support columns extend along the first direction, a first conductive structure is located on a first side of the channel structure along a second direction, the second direction is intersected with the first direction, a second conductive structure is located on the first side, and at least one support column is arranged between the first conductive structure and the second conductive structure. In some embodiments, the first conductive structure comprises a conductive part and a conductive block, wherein the conductive part comprises a conductive column and an insulating layer, the conductive column and the insulating layer extend along the first direction, the insulating layer is arranged around the conductive column, the conductive block is positioned on one side of the conductive part along the first direction, the conductive block extends along the second direction and the third direction, the conductive block is connected with the conductive column, and the third direction is intersected with a plane where the first direction and the second direction are located. In some embodiments, the conductive portion and the plurality of support columns are arranged along a second direction, and the conductive portion and the plurality of support columns are arranged along a third direction. In some embodiments, the conductive portion has a dimension in the second direction that is the same as the dimension of the support post in the second direction on a reference surface and/or the conductive portion has a dimension in the third direction that is the same as the dimension of the support post in the third direction on the reference surface, the reference surface intersecting the first direction. In some embodiments, the first conductive structure includes a plurality of conductive portions, the plurality of conductive portions being connected to the same conductive block. In some embodiments, in the second direction, the support columns adjacent to the conductive portion are first sub-columns, a distance between the first sub-columns and the conductive portion is a first distance, and a distance between two adjacent support columns is equal to the first distance. In some embodiments, in the third direction, the support columns adjacent to the conductive portion are second sub-columns, a distance between the second sub-columns and the conductive portion is a second distance, and a distance between two adjacent support columns is equal to the second distance. In some embodiments, in the second direction, a spacing between adjacent two of the support posts is equal to a spacing between adjacent two of the conductive portions. In some embodiments, in the third direction, a pitch between two adjacent support columns is equal to a pitch between two adjacent conductive portions. In some embodiments, any of the support posts are located between the conductive portion and the channel structure in the second direction, or between the conductive portion and the channel structure in the third direction. In some embodiments, in the first direction, the conductive block covers at least one support post. In some embodiments, the dimensions of the conductive portion in the second direction and the dimensions of the conductive portion in the third direction are each less than 150nm. In some embodiments, the semiconductor structure comprises a plurality of first conductive structures, the plurality of first conductive structures are arranged at intervals, and the minimum distance between adjacent conductive blocks is larger than 3 mu m. In some embodiments, the semiconductor device further comprises a first gate isolation structure and a second gate