CN-122002809-A - Semiconductor device and electronic system including the same

Abstract

A semiconductor device may include an element isolation film on a substrate, a first gate electrode, and an auxiliary electrode on the element isolation film. The element isolation film may define a first active region of the substrate. First and second source/drain regions of the first conductivity type may be in the first active region. The second source/drain region may be spaced apart from the first source/drain region in the first direction. The first gate electrode may be on a portion of the first active region between the first source/drain region and the second source/drain region. The first gate electrode may extend in a second direction crossing the first direction. The substrate may include an impurity region surrounding the element isolation film. The impurity region may contain a second conductivity type impurity. The auxiliary electrode and the impurity region may be electrically connected to each other.

Inventors

• JIN DONGKUI
• WU JUNSHUO
• LI SHIXUN
• ZHANG SHENGBI

Assignees

• 三星电子株式会社

Dates

Publication Date

20260508

Application Date

20251104

Priority Date

20241104

Claims (20)

1. 1. A semiconductor device, comprising: A substrate; An element isolation film on the substrate, wherein the element isolation film defines a first active region of the substrate, the first active region of the substrate including a first source/drain region and a second source/drain region in the first active region, the first source/drain region contacting the element isolation film in a first direction and having a first conductivity type, the second source/drain region being spaced apart from the first source/drain region in the first direction and having the first conductivity type; A first gate electrode on a portion of the first active region between the first source/drain region and the second source/drain region, wherein the first gate electrode extends in a second direction, the second direction intersecting the first direction; A second gate electrode on the first active region and extending in the second direction, wherein the second source/drain region is between the first gate electrode and the second gate electrode, and A first auxiliary electrode on the element isolation film, Wherein the first auxiliary electrode does not overlap the first source/drain region in the second direction in a plan view, and the first auxiliary electrode overlaps the second source/drain region in the second direction.
2. 2. The semiconductor device according to claim 1, wherein the first auxiliary electrode is applied with a ground voltage.
3. 3. The semiconductor device of claim 1, wherein, The substrate further includes an impurity region in the substrate, and the impurity region surrounds the element isolation film, The impurity region contains an impurity having a second conductivity type, and The second conductivity type is different from the first conductivity type.
4. 4. The semiconductor device according to claim 3, wherein, in a plan view, The first auxiliary electrode is between the second source/drain region and the impurity region.
5. 5. The semiconductor device according to claim 3, further comprising: A connection pattern connecting the first auxiliary electrode and the impurity region to each other, Wherein the impurity region is applied with a ground voltage.
6. 6. The semiconductor device according to claim 3, wherein, The first conductivity type is n-type, and The second conductivity type is p-type.
7. 7. The semiconductor device according to claim 1, wherein the first gate electrode and the first auxiliary electrode do not overlap each other in the first direction.
8. 8. The semiconductor device according to claim 1, wherein the first gate electrode and the first auxiliary electrode do not overlap each other in the second direction.
9. 9. The semiconductor device of claim 1, wherein the first gate electrode and the first auxiliary electrode are at a same height.
10. 10. The semiconductor device of claim 1, wherein, The first active region of the substrate further includes a third source/drain region in the first active region, The third source/drain region being in contact with the element isolation film in the first direction, and the third source/drain region having the first conductivity type, The second gate electrode is on a portion of the first active region between the second source/drain region and the third source/drain region, and In the plan view, the first auxiliary electrode does not overlap the third source/drain region in the second direction.
11. 11. The semiconductor device of claim 1, further comprising: A third gate electrode, and A second auxiliary electrode on the element isolation film, wherein, The first active region of the substrate further includes third and fourth source/drain regions in the first active region, The third source/drain region being spaced apart from the second source/drain region in the first direction, and the third source/drain region having the first conductivity type, The fourth source/drain region being spaced apart from the third source/drain region in the first direction, The fourth source/drain region contacts the element isolation film in the first direction, and the fourth source/drain region has the first conductivity type, The third gate electrode is on a portion of the first active region between the third source/drain region and the fourth source/drain region, The third gate electrode extends in the second direction, and In the plan view, the second auxiliary electrode overlaps the third source/drain region in the second direction and does not overlap the fourth source/drain region in the second direction.
12. 12. The semiconductor device of claim 11, wherein the second auxiliary electrode is spaced apart from the first auxiliary electrode in the first direction.
13. 13. The semiconductor device of claim 11, wherein the first auxiliary electrode and the second auxiliary electrode are at the same height.
14. 14. The semiconductor device of claim 1, further comprising: A unit substrate spaced apart from the substrate in a vertical direction, the vertical direction intersecting an upper surface of the substrate; a plurality of word lines sequentially stacked on the cell substrate; a channel structure on the cell substrate, the channel structure intersecting the plurality of word lines, and A bit line contacting the channel structure, Wherein the first source/drain region is electrically connected to one of the plurality of word lines.
15. 15. A semiconductor device, comprising: A substrate; An element isolation film on the substrate, wherein the element isolation film defines a first active region of the substrate, the first active region of the substrate including a first source/drain region and a second source/drain region in the first active region, the first source/drain region having a first conductivity type, the second source/drain region being spaced apart from the first source/drain region in a first direction and having the first conductivity type; a first gate electrode on a portion of the first active region between the first source/drain region and the second source/drain region, wherein the first gate electrode extends in a second direction, and the second direction intersects the first direction; An auxiliary electrode on the element isolation film, wherein, The substrate includes an impurity region surrounding the element isolation film, The impurity region includes an impurity having a second conductivity type, The second conductivity type is different from the first conductivity type, and The auxiliary electrode and the impurity region are electrically connected to each other.
16. 16. The semiconductor device according to claim 15, wherein a ground voltage is applied to the auxiliary electrode and the impurity region.
17. 17. The semiconductor device of claim 15, further comprising: A second gate electrode, wherein, The first active region further includes a third source/drain region in the first active region, the third source/drain region being in contact with the element isolation film in the first direction, and the third source/drain region having the first conductivity type, The second gate electrode is on a portion of the first active region between the second source/drain region and the third source/drain region, The second gate electrode extends in the second direction, The auxiliary electrode does not overlap the third source/drain region in the second direction in a plan view.
18. 18. The semiconductor device according to claim 17, wherein the auxiliary electrode is between the second source/drain region and the impurity region in the plan view.
19. 19. The semiconductor device of claim 15, further comprising: A unit substrate spaced apart from the substrate in a vertical direction, the vertical direction intersecting an upper surface of the substrate; a plurality of word lines sequentially stacked on the cell substrate; A channel structure on the cell substrate and intersecting the plurality of word lines, and A bit line contacting the channel structure, Wherein the first source/drain region is electrically connected to one of the plurality of word lines.
20. 20. An electronic system, comprising: A main substrate; A semiconductor device including a first substrate having a peripheral circuit region and a second substrate having a cell region on the main substrate, and A main controller on the main substrate and electrically connected to the semiconductor device, wherein, The semiconductor device includes an element isolation film on the first substrate, a first gate electrode, a second gate electrode, an auxiliary electrode on the element isolation film, a plurality of word lines sequentially stacked on the second substrate, a channel structure on the second substrate and intersecting the plurality of word lines, and a bit line contacting the channel structure, wherein, The element isolation film defines a first active region in the substrate, The first active region includes a first source/drain region and a second source/drain region, The first source/drain region contacts the element isolation film in a first direction and has a first conductivity type, The second source/drain region being spaced apart from the first source/drain region in the first direction and having the first conductivity type, The first gate electrode is on a portion of the first active region between the first source/drain region and the second source/drain region, The first gate electrode extends in a second direction, the second direction intersecting the first direction, The second gate electrode extends over the first active region and in the second direction, The second source/drain region is between the first gate electrode and the second gate electrode, and The auxiliary electrode does not overlap the first source/drain region in the second direction, and the auxiliary electrode overlaps the second source/drain region in the second direction in plan view.

Description

Semiconductor device and electronic system including the same Cross Reference to Related Applications The present application claims priority from korean patent application No.10-2024-0154177, filed on the korean intellectual property office at 11/4/2024, the entire contents of which are incorporated herein by reference. Technical Field The present disclosure relates to a semiconductor device and an electronic system including the semiconductor device. More particularly, the present disclosure relates to a semiconductor device including three-dimensionally arranged memory cells and/or an electronic system including the semiconductor device. Background As electronic products become lighter, thinner, and more compact, the demand for high integration of semiconductor devices is increasing. As semiconductor devices become more highly integrated, the size of components (e.g., transistors) in the semiconductor devices may be further reduced, resulting in leakage currents. Accordingly, it is desirable to control the leakage current of semiconductor devices to improve the performance and/or reliability of the semiconductor devices. In an electronic system requiring data storage, there is a need for a semiconductor device capable of storing large-capacity data therein. Accordingly, a scheme of increasing the data storage capacity of the semiconductor device is being studied. For example, in a method for improving the data storage capacity of a semiconductor device, a semiconductor device including memory cells arranged in three dimensions instead of memory cells arranged in two dimensions has been proposed. Disclosure of Invention The present disclosure relates to a semiconductor device having improved performance and reliability. The present disclosure relates to an electronic system including a semiconductor device with improved performance and reliability. Aspects of the present disclosure are not limited to the above-described aspects, and other aspects not mentioned may be clearly understood by those skilled in the art from the description set forth below. According to an embodiment of the present disclosure, a semiconductor device may include an element isolation film on a substrate, the element isolation film defining a first active region of the substrate including a first source/drain region and a second source/drain region in the first active region, the first source/drain region contacting the element isolation film in a first direction and having a first conductivity type, the second source/drain region being spaced apart from the first source/drain region in the first direction and having the first conductivity type, a first gate electrode on a portion of the first active region between the first source/drain region and the second source/drain region, wherein the first gate electrode extends in a second direction and intersects the first direction, a second gate electrode on the first active region and extending in the second direction, wherein the second source/drain region is between the first gate electrode and the second gate electrode, and a first auxiliary electrode on the element isolation film. The first auxiliary electrode may not overlap the first source/drain region in the second direction in a plan view, and the first auxiliary electrode may overlap the second source/drain region in the second direction. According to an embodiment of the present disclosure, a semiconductor device may include a substrate, an element isolation film on the substrate, the element isolation film defining a first active region of the substrate, the first active region of the substrate including a first source/drain region and a second source/drain region in the first active region, the first source/drain region having a first conductivity type, the second source/drain region being spaced apart from the first source/drain region in a first direction and having the first conductivity type, a first gate electrode on a portion of the first active region between the first source/drain region and the second source/drain region, wherein the first gate electrode extends in a second direction and intersects the first direction, and an auxiliary electrode on the element isolation film. The substrate may include an impurity region surrounding the element isolation film. The impurity region may include an impurity having a second conductivity type. The second conductivity type may be different from the first conductivity type, and the auxiliary electrode and the impurity region may be electrically connected to each other. According to an embodiment of the present disclosure, an electronic system may include a main substrate, a semiconductor device on the main substrate, the semiconductor device including a first substrate having a peripheral circuit region and a second substrate having a cell region, and a main controller on the main substrate and electrically connected to the semiconductor device. The semiconductor device ma