CN-122002810-A - Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device and a method of manufacturing the same are provided, the method including providing a substrate on which a transistor is formed, forming a first dielectric layer covering the transistor, forming a patterned electrode layer on the first dielectric layer, etching the electrode layer to separate the electrode layer into a first electrode layer and a second electrode layer isolated from each other while forming a gap in the electrode layer, wherein the first electrode layer is electrically connected to the transistor, and filling a capacitance dielectric layer in the gap to form a capacitor composed of the first electrode layer, the capacitance dielectric layer, and the second electrode layer. The electrode layer is divided into the first electrode layer and the second electrode layer by forming a gap in the electrode layer, then the capacitor medium layer is filled in the gap to form a capacitor formed by the first electrode layer, the capacitor medium layer and the second electrode layer, and the coverage area and the current polarization intensity of the capacitor medium layer are increased by the gap in the electrode layer, so that the residual polarization amount of the capacitor is improved, and the durability of the semiconductor device is improved.

Inventors

• LI HONGBO
• JIN XINGCHENG

Assignees

• 无锡华润微电子有限公司

Dates

Publication Date

20260508

Application Date

20241105

Claims (10)

1. 1. A method of manufacturing a semiconductor device, comprising: Providing a substrate, wherein a transistor is formed on the substrate; forming a first dielectric layer covering the transistor; Forming a patterned electrode layer on the first dielectric layer; Etching the electrode layer to separate the electrode layer into a first electrode layer and a second electrode layer isolated from each other while forming a slit in the electrode layer, wherein the first electrode layer is electrically connected to the transistor; and filling a capacitance medium layer in the gap to form a capacitor formed by the first electrode layer, the capacitance medium layer and the second electrode layer.
2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the electrode layer is etched using a deep reactive ion etching process to form the slit in the electrode layer.
3. 3. The method of manufacturing a semiconductor device according to claim 1, wherein forming a patterned electrode layer on the first dielectric layer comprises forming a second dielectric layer on the first dielectric layer to cover the first dielectric layer, etching the second dielectric layer to form a patterned trench in the second dielectric layer, filling an electrode material layer in the trench, and removing the electrode material layer outside the trench to form the patterned electrode layer.
4. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the slit has a curved serpentine shape.
5. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the electrode layer comprises titanium nitride and the capacitor dielectric layer comprises a ferroelectric material.
6. 6. The method for manufacturing a semiconductor device according to claim 1, wherein a conductive plug electrically connected to a drain of the transistor is formed in the first dielectric layer, and the first electrode layer covers a top surface of the conductive plug.
7. 7. A semiconductor device, comprising: A substrate; a transistor on the substrate; A first dielectric layer on the substrate and covering the transistor; A first electrode layer and a second electrode layer on the first dielectric layer, wherein the first electrode layer is electrically connected to the transistor; the capacitor comprises a first electrode layer, a second electrode layer, a gap between the first electrode layer and the second electrode layer, wherein a capacitance medium layer is filled in the gap, the first electrode layer, the capacitance medium layer and the second electrode layer form a capacitor, and the heights of the first electrode layer, the capacitance medium layer and the second electrode layer are the same.
8. 8. The semiconductor device of claim 7, wherein the first electrode layer and the second electrode layer comprise titanium nitride and the capacitive dielectric layer comprises a ferroelectric material.
9. 9. The semiconductor device of claim 7, wherein the slit has a serpentine shape.
10. 10. The semiconductor device according to claim 7, wherein a conductive plug electrically connected to a drain of the transistor is formed in the first dielectric layer, and the first electrode layer covers a top surface of the conductive plug.

Description

Semiconductor device and manufacturing method thereof Technical Field The application relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof. Background Ferroelectric memory (FRAM) is a new type of memory, which has both the non-volatility of ROM and RAM, and has the advantages of strong endurance, high-speed reading and writing, low power consumption, etc., and is widely used in various fields. In the related art, the HZO ferroelectric capacitor generally adopts an MFM (Metal-Ferroelectric-Metal) structure, i.e., an HZO ferroelectric is disposed between two Metal electrodes. Compared with the traditional ferroelectric materials (such as PZT) which are commercialized, the HZO ferroelectric capacitor has obvious advantages in terms of expansibility and read-write speed, and is more consistent with the development path of high speed and miniaturization of a semiconductor device, however, after being polarized for a plurality of times, the HZO ferroelectric has faster polarization reduction speed, reduced residual polarization amount and seriously affects the durability of the HZO ferroelectric. Disclosure of Invention In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. The summary of the application is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. In view of the problems existing at present, an aspect of the present application provides a method for manufacturing a semiconductor device, including: Providing a substrate, wherein a transistor is formed on the substrate; forming a first dielectric layer covering the transistor; Forming a patterned electrode layer on the first dielectric layer; Etching the electrode layer to separate the electrode layer into a first electrode layer and a second electrode layer isolated from each other while forming a slit in the electrode layer, wherein the first electrode layer is electrically connected to the transistor; and filling a capacitance medium layer in the gap to form a capacitor formed by the first electrode layer, the capacitance medium layer and the second electrode layer. Illustratively, the electrode layer is etched using a deep reactive ion etching process to form the gap in the electrode layer. Illustratively, the forming a patterned electrode layer on the first dielectric layer includes forming a second dielectric layer overlying the first dielectric layer on the first dielectric layer, etching the second dielectric layer to form a patterned trench in the second dielectric layer, filling an electrode material layer in the trench, and removing the electrode material layer outside the trench to form the patterned electrode layer. Illustratively, the slit is serpentine in shape. Illustratively, the electrode layer comprises titanium nitride and the capacitive dielectric layer comprises a ferroelectric material. Illustratively, a conductive plug electrically connected to the drain of the transistor is formed in the first dielectric layer, and the first electrode layer covers a top surface of the conductive plug. In another aspect, the present application provides a semiconductor device comprising: A substrate; a transistor on the substrate; A first dielectric layer on the substrate and covering the transistor; A first electrode layer and a second electrode layer on the first dielectric layer, wherein the first electrode layer is electrically connected to the transistor; The capacitor comprises a first electrode layer, a second electrode layer, a gap between the first electrode layer and the second electrode layer, and a capacitor formed by the first electrode layer, the capacitor dielectric layer and the second electrode layer, wherein the gap is filled with a capacitor dielectric layer, and the heights of the first electrode layer, the capacitor dielectric layer and the second electrode layer are the same. Illustratively, the first electrode layer and the second electrode layer comprise titanium nitride and the capacitive dielectric layer comprises a ferroelectric material. Illustratively, the slit is serpentine in shape. Illustratively, a conductive plug electrically connected to the drain of the transistor is formed in the first dielectric layer, and the first electrode layer covers a top surface of the conductive plug. According to the semiconductor device and the manufacturing method thereof, the gap is formed in the patterned electrode layer, the electrode layer is divided into the first electrode layer and the second electrode layer, then the capacitor dielectric layer is filled in the gap to form the capacitor formed by the first electrode layer, the capacitor dielectric layer and the second electrode layer, and the coverage area and the current polarizat