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CN-122002811-A - CMOS three-dimensional memory architecture and preparation method thereof

CN122002811ACN 122002811 ACN122002811 ACN 122002811ACN-122002811-A

Abstract

The invention discloses a CMOS three-dimensional memory architecture and a preparation method thereof, and belongs to the technical field of integrated circuits. The CMOS three-dimensional memory architecture is characterized in that one or more 2FnSnR memory units are built on a base comprising a double-finger transistor (2F), each 2FnSnR memory unit comprises a double-finger transistor and n parallel 1S1R memory units, the double-finger transistor adopts a common-source common-drain structure, a drain electrode is led out, a source electrode is led out, two grid electrodes are respectively led out to form a word line, one end electrode of each n 1S1R memory units is connected with the drain line, and the other end electrode is connected with the corresponding bit line to form a parallel connection relationship. In the architecture, the two-finger design can improve the control capability of the transistor, so that the transistor can maintain stable driving current and read-write characteristics when being connected with n 1S1R memory cells, and can remarkably improve the integration density of the memory cells and maintain excellent electrical performance.

Inventors

  • WANG ZONGWEI
  • CHEN YUJIE
  • CAI YIMAO
  • YANG GAOQI
  • HUANG RU

Assignees

  • 北京大学

Dates

Publication Date
20260508
Application Date
20241107

Claims (10)

  1. 1. A CMOS three-dimensional memory architecture is characterized in that one or more 2FnSnR memory units are built on a base comprising a double-finger transistor, each 2FnSnR memory unit comprises a double-finger transistor and n parallel 1S1R memory units, n is an integer greater than 1, the double-finger transistor adopts a common source common drain structure, a drain electrode is led out, a source electrode is led out, two grid electrodes are respectively led out of a word line, one end electrode of each n 1S1R memory units is connected with the drain line, and the other end electrode is connected with the corresponding bit line to form a parallel connection.
  2. 2. The CMOS three-dimensional memory architecture of claim 1 wherein said base is formed with a plurality of two-finger transistors arranged in an xy horizontal plane, a multi-layer stack of 1S1R memory cells is made in the z direction, each layer containing at least one 1S1R memory cell, forming a three-dimensional memory architecture comprising a plurality of 2FnSnR memory cells, for each 2FnSnR memory cell, a plurality of 1S1R memory cells in the same layer are connected in parallel by horizontal drain lines, and 1S1R memory cells in different layers are electrically connected vertically by inter-layer vias.
  3. 3. The CMOS three-dimensional memory architecture of claim 2, wherein the plurality of two-finger transistors on the base are arranged in an array, each two-finger transistor forming a 2FnSnR memory cell with n parallel 1S1R memory cells stacked in layers above it, the two-finger transistors of adjacent 2FnSnR memory cells sharing a source line in the y-direction, the two-finger transistors of adjacent 2FnSnR memory cells sharing a source line and a word line in the x-direction, and the plurality of 1S1R memory cells located in the same layer and aligned in the x-direction sharing a bit line.
  4. 4. The CMOS three-dimensional memory structure of claim 3 wherein the 1S1R memory cells of the same layer are aligned in the x and y directions and the 1S1R memory cells of adjacent layers are staggered and connected to the drains of the two-finger transistors on the base through vias in the z direction.
  5. 5. A method for fabricating the CMOS three-dimensional memory architecture of any one of claims 1-4, comprising the steps of: S1, preparing a base containing a double-finger transistor based on a CMOS (complementary metal oxide semiconductor) process, and opening a word line led out from a grid electrode of the double-finger transistor along the x direction; S2, depositing a second insulating dielectric layer on the first insulating dielectric layer, imaging, depositing a source line in the second insulating dielectric layer along the x direction, and depositing a drain line to lead out the drain electrode of the double-finger transistor on the base; S3, depositing a third insulating medium layer on the second insulating medium layer, and imaging, wherein a first through hole is formed in the third insulating medium layer so as to be in contact with a drain wire in the second insulating medium layer; S4, depositing a fourth insulating medium layer on the third insulating medium layer, imaging, setting a bit line on the fourth insulating medium layer along the x direction, and setting a drain line to be in contact with the first through hole; S5, depositing a fifth insulating medium layer on the fourth insulating medium layer, imaging, arranging a 1S1R storage unit in the fifth insulating medium layer, and arranging a second through hole to be in contact with a drain line in the third insulating medium layer; S6, depositing a sixth insulating medium layer on the fifth insulating medium layer, imaging, setting bit lines on the sixth insulating medium layer along the x direction, setting drain lines along the y direction, and enabling the drain lines to be in contact with the second through holes in the fifth insulating medium layer and all 1S1R memory cells to form electric parallel connection; And repeating the steps S5-S6 for m times, wherein m is more than or equal to 1, and only setting a drain line and no bit line when the last step S6 is carried out, thereby completing the preparation of the CMOS three-dimensional memory architecture.
  6. 6. The method of claim 5, wherein the low-k dielectric material is deposited as an insulating dielectric layer by a chemical vapor deposition process in steps S1-S6, and the planarization process is performed by a chemical mechanical polishing process after each layer is deposited.
  7. 7. The method of claim 6, wherein the low dielectric constant material is selected from one or more of SiO 2 , siCOH, USG, BPSG, and the deposited dielectric layer has a thickness of 20-2500nm.
  8. 8. The method of claim 5, wherein the source, drain, bit and word line materials are selected from one or more of V, nb, ru, W, ta, taN, ti, tiN, tiW, al, tiAlW, tiAlN, alO x , hf, ir, mn, zn, pd, cu, or doped polysilicon materials, and the via and via materials are selected from one or more of Cu, W, al, tiN, taN, tiW, tiAlW.
  9. 9. The method of claim 5, wherein in the step S5, a 1S1R memory cell is formed by providing a gating layer and a resistive layer or providing a self-selection layer, wherein the gating layer or the self-selection layer is made of niobium oxide and/or vanadium oxide; the material of the resistance change layer is selected from tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide and silicon oxide.
  10. 10. The method for operating a CMOS three-dimensional memory architecture according to any one of claims 1 to 4, wherein the read-write and erase operations are implemented by applying an operating voltage to a bit line corresponding to a selected 1S1R memory cell and turning on a double-finger transistor on a base through a word line, so that the 1S1R memory cell is turned on with a drain and a source.

Description

CMOS three-dimensional memory architecture and preparation method thereof Technical Field The invention belongs to the technical field of semiconductor and CMOS hybrid integrated circuits, and particularly relates to a novel memory (emerging memory) framework compatible with the existing CMOS process and integrated with CMOS and a preparation method thereof. Background With the rapid development of new generation information technologies such as 5G, artificial Intelligence (AI), internet of things (IoT), etc., massive and diversified data needs to be stored and processed efficiently, and the demand for semiconductor memories has been in a rapidly growing trend. In mobile terminal devices (e.g., wearable devices) that are currently in widespread use, embedded storage is evolving toward small-sized, large-capacity devices. However, the nonvolatile memory represented by Flash encounters a bottleneck in the 40nm process node, and the planar integrated architecture is difficult to further increase the storage density, so that the requirement of the mobile internet era on high-density storage cannot be met. A Resistive Random Access Memory (RRAM), which is one of the new memories, is considered as a key technology capable of continuing the scaling to 22nm and below, and provides a non-volatile memory solution for 28nm and below. In RRAM arrays, word lines and bit lines are cross-connected (Crossbar structure), which is susceptible to leakage current during reading in high density memory arrays. The leakage current is mainly derived from the disturb current of the adjacent memory cells and may lead to read and program errors. Therefore, in high density memory arrays, how to accurately access a target memory cell with anti-disturb capability is a major challenge. To solve the above problem, a common design is a 1T1R structure in which a transistor (T) acts as a gating unit, effectively turning off the leakage path. However, in this structure, the area of each memory cell is 6F2 (F is the feature size), and the three-terminal design of the MOSFET device limits the high density advantage of RRAM and is not suitable for three-dimensional stacked architecture. Another design to address the side leakage current is a 1S1R structure, where the RRAM is connected to a gate tube (Selector) with threshold transition characteristics. Each memory cell area of the structure is determined by the overlapping portion of the word line and the bit line, and the minimum area can reach 4F2. In addition, the design supports multi-layer stacking, so that the effective area of each memory cell is reduced to 4F2/N (N is the number of stacking layers), and high-density three-dimensional integration is realized. The combination of the two techniques induced a 1TnSnR structure. The structure is formed by connecting a MOSFET base and a plurality of 1S1R memory cells in parallel. Compared with the traditional 1T1R structure, the 1TnSnR controls a plurality of memory cells through a single MOSFET, effectively improves the memory density, reduces the cell area and maintains excellent read-write performance. In the aspect of three-dimensional integration, 1TnSnR shows remarkable advantages, can stack a plurality of layers of memory cells, reduces leakage current and crosstalk problems, improves overall stability and memory efficiency, and is suitable for application of high-density memories such as RRAM. Disclosure of Invention The invention provides a three-dimensional integrated architecture based on 2FnSnR and a process implementation method thereof, and aims to further improve the storage density of a Resistive Random Access Memory (RRAM), a phase change memory (PCRAM), a magneto-resistive memory (MRAM) and a ferroelectric memory (FeRAM) and optimize the structure and performance of a unit. Compared with the 1TnSnR structure, the 2FnSnR structure has the advantages that the integration density of the memory unit is remarkably improved and excellent electrical performance is maintained by adopting the double-finger transistor (see S.K.Gupta,S.P.Park,N.N.Mojumder and K.Roy,"Layout-aware optimization of stt mrams,"2012Design,Automation&Test in Europe Conference&Exhibition(DATE),Dresden,Germany,2012,pp.1455-1458,doi:10.1109/DATE.2012.6176595.) design and innovative circuit connection mode. The three-dimensional memory architecture of the present invention is to construct one or more 2FnSnR memory cells on a base (2F base) comprising a Two-finger transistor (Two-Finger Transistor, 2F for short), each 2FnSnR memory cell comprising a Two-finger transistor structure and n parallel 1S1R memory cells, the 1S1R memory cells being connected by a common drain of the Two-finger transistor. The 1S1R memory cell is composed of a self-selection characteristic structure (S) and a resistance change structure (R). In this architecture, the two-finger transistor design can improve the control capability of the MOSFET so that it maintains stable drive current and r