CN-122002812-A - Multi-layer vertical stack type hundred million-resistance memory and manufacturing method thereof

CN122002812ACN 122002812 ACN122002812 ACN 122002812ACN-122002812-A

Abstract

The invention relates to a multilayer vertical stack hundred million-resistance memory and a manufacturing method thereof, belongs to the technical field of memories, and solves the problem of current crosstalk caused by density increase of the existing memory cells. The memory includes a bottom layer circuit over a semiconductor substrate and provided with a layer and column address switches, a bottom insulating layer over the bottom layer circuit in which a plurality of via holes are provided, a plurality of alternating stacks over the bottom layer circuit, each alternating stack including a planar conductive layer and an overlying interlayer insulating layer, a vertical pillar electrode passing through the plurality of alternating stacks to electrically connect with the plurality of via holes, a resistive medium layer surrounding a periphery of the vertical pillar electrode such that the planar conductive layer, the resistive medium layer, and the vertical pillar electrode constitute a resistive memory, and a region isolation trench including a plurality of rows and columns of parallel isolation trenches passing through the plurality of alternating stacks, the bottom insulating layer, and the bottom layer circuit to isolate the three-dimensional memory array into a plurality of memory cell regions. Inter-layer and inter-row current cross-talk is reduced by block division and insulation break.

Inventors

ZHANG FENG
Nie long
MA CAILIAN

Assignees

中国科学院微电子研究所

Dates

Publication Date: 20260508
Application Date: 20241107

Claims (10)

1. A multi-layer vertically stacked, multi-layer memory comprising: A semiconductor substrate; A bottom layer circuit located above the semiconductor substrate and provided with a layer addressing switch and a column addressing switch; A bottom insulating layer over the underlying circuitry, wherein a plurality of vias are disposed; a plurality of alternating stacks located above the underlying circuitry, each alternating stack comprising a planar conductive layer and an interlayer insulating layer located above the planar conductive layer; a vertical column electrode passing through the plurality of alternating stacks to be electrically connected with the plurality of through holes; A resistive medium layer surrounding the periphery of the vertical columnar electrode so that the planar conductive layer, the resistive medium layer and the vertical columnar electrode constitute a resistive memory, and And a region isolation trench including a plurality of rows of parallel isolation trenches and a plurality of columns of parallel isolation trenches, passing through the plurality of alternating stacks, the bottom insulating layer and the bottom layer circuit to isolate the three-dimensional memory array into a plurality of memory cell regions.
2. The multi-layer vertically stacked one hundred million memory of claim 1, wherein the memory cell region is rectangular, the plurality of alternating stacks are step-like alternating stacks, wherein, The H steps of the step-like alternating stack are located at opposite first and second sides of a rectangular memory cell region, wherein the first and second sides are parallel to a multi-column region isolation trench to expose first to H conductive layers of the plurality of alternating stacks from bottom to top through the H steps.
3. The multi-layer vertically stacked one hundred million memory of claim 2, further comprising a plurality of sets of row lines connected to said layer addressing switch, wherein each set of row lines has H lines, and wherein each set of row lines further comprises: h first metal vias located on the 1 st to H th steps at the first side, respectively; H second metal vias located on the 1 st to H th steps at the second side portion, respectively; H third metal vias located over the bottom circuit at the first side periphery and electrically connected to the metal layer in the bottom circuit; H fourth metal vias located above the bottom circuit at the second side periphery and electrically connected to the metal layers in the bottom circuit, wherein the H first metal vias, the H second metal vias, the H third metal vias, and the H fourth metal vias have top surfaces that are flush; h first metal wires for respectively connecting the H first metal vias with the corresponding H third metal vias, and And H second metal wires are used for respectively connecting the H second metal through holes with the corresponding H fourth metal through holes.
4. The multi-layer vertically stacked one hundred million memory device of claim 2, further comprising row spacers passing through said plurality of alternating stacks for isolating adjacent rows of memory cells in each layer of memory cells.
5. The multi-layer vertical stack memory of claim 2 further comprising a first metal layer and a second metal layer, wherein, The first metal layer is used for connecting the layer addressing switch in the bottom layer circuit with the plurality of groups of row lines in the vertical direction through the plurality of through holes and the first metal layer The second metal layer is used for connecting the column addressing switch with the vertical columnar electrode in the vertical direction through the through holes and the second metal layer.
6. The multi-layer vertically stacked multi-layer resistance by one memory of claim 2, wherein the memory capacity of each memory cell region is H layers by M rows by N columns, and each memory cell region is divided into M groups of memory cells having the same memory capacity, wherein H, M and N are integers greater than 1, Wherein the source of the corresponding first MOS transistor in the layer addressing switch of the adjacent group is connected and the source of the corresponding second MOS transistor in the column addressing switch of the adjacent group is connected.
7. The multi-layer vertically stacked one hundred million memory of claim 6, wherein said layer addressing switch and said column addressing switch comprise a plurality of first MOS transistors and a plurality of second MOS transistors, respectively, wherein, Each first MOS transistor comprises a first source electrode, a first grid electrode and a first drain electrode, wherein the first source electrode is connected with a word line of a corresponding layer, the first grid electrode is connected with a power line, and the first drain electrode is connected to one end of each row of memory cells in the corresponding layer; each second MOS transistor comprises a second source electrode, a second grid electrode and a second drain electrode, wherein the second source electrode is connected with a corresponding column bit line, the second grid electrode is connected with a power line, and the second drain electrode is connected to the other end of each layer of memory cells in the corresponding column of memory cells.
8. The multi-layer vertical stack resistance random access memory according to any of claims 1 to 7, wherein, The bottom insulating layer, the interlayer insulating layers in the plurality of alternating stacks and the region isolation trench are made of SiO 2 ; the material of the plane conducting layers in the plurality of alternate stacks is TiN; the material of the resistive medium layer is HfOx/TaOx, and The vertical columnar electrode is made of tungsten.
9. A method for fabricating a multi-layer vertically stacked multi-layer memory, comprising: Forming a bottom layer circuit over a semiconductor substrate, wherein the bottom layer circuit is provided with layer addressing switches and column addressing switches; Forming a bottom insulating layer over the underlying circuit, wherein a plurality of vias are provided in the bottom insulating layer; Forming a plurality of alternating stacks over the underlying circuitry, wherein each alternating stack includes a planar conductive layer and an interlayer insulating layer over the planar conductive layer; Etching the plurality of alternating stacks and the bottom insulating layer to form a plurality of rows of parallel isolation trenches and a plurality of columns of parallel isolation trenches and filling with insulating material to isolate the three-dimensional memory array into a plurality of memory cell regions; etching the plurality of alternating stacks to form a plurality of vertical pillar holes to expose top surfaces of the plurality of vias, and Forming a uniform resistive medium layer on the inner walls of the plurality of vertical columnar holes, and The plurality of vertical pillar holes are filled with a metal material to form a vertical pillar electrode such that the planar conductive layer, the resistive medium layer, and the vertical pillar electrode constitute a resistive memory.
10. The multi-layered vertical of claim 9A method for manufacturing a stacked one hundred million-resistance memory, it is characterized in that the method comprises the steps of, After etching the plurality of alternating stacks and the bottom insulating layer to form the plurality of rows of parallel isolation trenches and the plurality of columns of parallel isolation trenches and before filling with insulating material, further comprising: Etching the plurality of alternating stacks from top to bottom to form H steps at first and second opposite sides of the memory cell region, respectively, wherein the first and second sides are parallel to the multi-column region isolation trenches to expose the first to H conductive layers of the plurality of alternating stacks from bottom to top through the H steps; the method further comprises the following steps of: forming H first holes on top surfaces of the 1 st to H th steps at the first side portion, respectively, and filling a metal material to form H first metal vias; Forming H second holes on top surfaces of the 1 st to H th steps at the second side portion, respectively, and filling a metal material to form H second metal vias; Forming H third holes aligned with the H first metal vias in a horizontal direction at the first side periphery, respectively, and filling a metal material to form a column of H third metal vias, wherein the H third metal vias are electrically connected with the metal layer in the bottom circuit; Forming H fourth holes aligned with the H second metal vias in a horizontal direction at the second side periphery, respectively, and filling a metal material to form a column of H fourth metal vias, wherein the H third metal vias are electrically connected with the metal layer in the bottom circuit, and top surfaces of the H first metal vias, the H second metal vias, the H third metal vias and the H fourth metal vias are flush; forming H first metal wires above the H first metal vias and the H third metal vias, and And forming H second metal wires above the H second metal vias and the H fourth metal vias.

Description

Multi-layer vertical stack type hundred million-resistance memory and manufacturing method thereof Technical Field The invention relates to the technical field of memories, in particular to a multilayer vertical stack type hundred million-resistance memory and a manufacturing method thereof. Background In existing two-dimensional planar memories, storage density and performance have approached physical limits. Three-dimensional vertical stacking techniques are widely studied to overcome these limitations. However, as the density of memory cells increases, current cross-talk becomes increasingly serious, directly affecting the stability and reliability of the memory, while larger transmission distances lead to increased losses and errors, and three-dimensional memristive memories and peripheral circuits have a major disadvantage in connection through board levels. Therefore, it is particularly important to design a fully integrated vertically stacked memristive memory chip that is capable of effectively reducing crosstalk. The three-dimensional memristor (3D RRAM) is divided into a horizontal stacking scheme and a vertical stacking scheme, wherein the horizontal stacking integrated structure is a scheme that the structure is in a vertical arrangement mode of a multi-layer two-dimensional Crossbar array, the Crossbar array has good characteristics, the device can be regarded as discrete, and the problem of current crosstalk can be effectively avoided between units. However, since multiple photolithography is required and the cost of the photolithography process increases exponentially with the number of layers, the crossbar structure is not used for design. And manufacturing the 3D RRAM array by selecting a three-dimensional vertical stacking structure. Disclosure of Invention In view of the above, the present invention provides a multi-layer vertical stacked multi-layer memory and a method for fabricating the same, which are used for solving the current cross-talk problem caused by the density increase of the existing memory cells. In one aspect, embodiments of the present invention provide a multi-layer vertical stack type resistance-by-one memory including a semiconductor substrate, a bottom layer circuit over the semiconductor substrate and provided with layer addressing switches and column addressing switches, a bottom insulating layer over the bottom layer circuit in which a plurality of through holes are provided, a plurality of alternating stacks over the bottom layer circuit, each alternating stack including a planar conductive layer and an interlayer insulating layer over the planar conductive layer, vertical pillar electrodes passing through the plurality of alternating stacks and electrically connected to the plurality of through holes, a resistance-changing dielectric layer surrounding a periphery of the vertical pillar electrodes such that the planar conductive layer, the resistance-changing dielectric layer, and the vertical pillar electrodes constitute a resistance-changing memory, and region isolation trenches including a plurality of rows of parallel isolation trenches and a plurality of columns of parallel isolation trenches passing through the plurality of alternating stacks, the bottom insulating layer, and the bottom layer circuit to isolate a three-dimensional memory array into a plurality of memory cell regions. The technical scheme has the beneficial effects that through reasonable block division and insulation partition design, the problem of current crosstalk between layers and between rows is effectively reduced, and the stability and reliability of data are ensured. The storage density of a single chip is greatly improved through eight-layer stacking, so that more data can be stored in a limited space. Based on a further improvement of the above device, the plurality of alternating stacks are step-like alternating stacks, wherein the H steps of the step-like alternating stacks are located at opposite first and second sides of the rectangular memory cell region, wherein the first and second sides are parallel to the multi-column region isolation trenches to expose the first to H conductive layers of the plurality of alternating stacks from bottom to top through the H steps. Based on a further improvement of the device, the multi-layer vertical stacking type multi-layer resistance memory further comprises a plurality of groups of row lines connected with the layer addressing switch, wherein each group of row lines has H pieces, and each group of row lines further comprises H first metal through holes which are respectively positioned on the 1 st to H th steps at the first side part; the semiconductor device comprises a first side part, a second side part, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, H second metal vias, H third metal vias, H first metal wires and H second metal wires, wherein the first side part is positioned on a1 st step to