CN-122002813-A - Memory structure and forming method thereof

Abstract

A memory structure and a forming method thereof comprise the steps of doping a substrate to form a word line doping layer in the substrate, doping the substrate on the word line doping layer or an epitaxial layer on the surface of the substrate to form a diode material layer on the word line doping layer, etching the substrate, the word line doping layer and the diode material layer to form a plurality of isolation openings, exposing the substrate of an isolation region from the isolation openings, doping the substrate exposed from the isolation openings, and forming an isolation doping region in the isolation region. When the substrate leaks electricity, the word line doped layer and the substrate of the isolation doped region form a reverse bias PN junction, so that the leakage current is cut off, the problem of substrate leakage is solved, the depth of the isolation opening is smaller, the process difficulty of etching the isolation opening is reduced, in addition, the memory structure can realize higher-density integration without larger modification, the number of diode units controlled by the word line doped layer is increased, and the performance of the memory structure is improved.

Inventors

• HAO NING
• ZHANG WEI
• WANG XUEYAN
• WANG XINDI
• LIU XINLI
• GUO DELIANG

Assignees

• 中芯京城集成电路制造(北京)有限公司
• 北方集成电路技术创新中心(北京)有限公司
• 中芯国际集成电路制造(上海)有限公司

Dates

Publication Date

20260508

Application Date

20241108

Claims (15)

1. 1. A method of forming a memory structure, comprising: providing a substrate, wherein the substrate comprises a plurality of active areas and isolation areas positioned between adjacent active areas; Doping the substrate to form a word line doping layer positioned in the substrate, wherein the word line doping layer is provided with first doping ions; Doping the substrate positioned on the word line doping layer or the epitaxial layer on the surface of the substrate to form a diode material layer positioned on the word line doping layer; Etching the substrate, the word line doping layer and the diode material layer to form a plurality of isolation openings, wherein the isolation openings expose the substrate of the isolation region; And carrying out doping treatment on the substrate exposed by the isolation opening, forming an isolation doped region in the isolation region, wherein second doping ions are arranged in the isolation doped region, and the conductivity type of the first doping ions is opposite to that of the second doping ions.
2. 2. The method of claim 1, wherein the substrate has a conductivity type comprising a P-type, the second dopant ion has a conductivity type comprising a P-type, and the substrate has a conductivity type that is the same as the conductivity type of the second dopant ion.
3. 3. The method of claim 1, wherein the substrate has a conductivity type comprising an N-type, the second dopant ion has a conductivity type comprising an N-type, and the substrate has a conductivity type that is the same as the conductivity type of the second dopant ion.
4. 4. The method of claim 1, wherein the isolation doped region has an ion doping concentration greater than an ion doping concentration of the substrate, wherein the second dopant ion has an ion doping concentration in a range of 1E10 atoms/cm 2 ～1E15atom/cm 2 , and wherein the substrate has an ion doping concentration in a range of 1E10 atoms/cm 2 ～1E15atom/cm 2 .
5. 5. The method of claim 1, wherein the first dopant ion conductivity type comprises a P-type or an N-type, and wherein the first dopant ion conductivity type is opposite to the substrate conductivity type.
6. 6. The method of claim 1, wherein the first dopant ions have an ion doping concentration in a range of 1E10 atoms/cm 2 ～1E15atom/cm 2 .
7. 7. The method of forming a memory structure of claim 1, wherein the isolation opening has a depth ranging from
8. 8. The method of claim 1, wherein forming the isolation opening comprises forming a mask layer on the surface of the diode material layer, wherein the mask layer exposes a portion of the surface of the diode material layer, and etching the diode material layer, the word line doped layer and the substrate with the mask layer as a mask until the surface of the substrate is exposed to form the isolation opening.
9. 9. The method of forming a memory structure of claim 1, wherein an ion doping concentration of the wordline doped layer is greater than an ion doping concentration of the diode material layer.
10. 10. The method of forming a memory structure of claim 1, wherein the active region and the isolation region are sequentially aligned along the X-direction.
11. 11. The method of claim 10, further comprising forming an isolation structure in the isolation region after forming the isolation doped region, forming a plurality of diode isolation openings in the isolation structure, the diode material layer, and the word line doped layer after forming the isolation structure, the diode isolation openings being aligned in a Y direction perpendicular to the X direction, forming a diode isolation structure in the diode isolation openings, doping the diode material layer to form a plurality of diode cells separated from each other on a surface of the word line doped layer, forming a first conductive plug on a surface of each of the diode cells, and forming a bit line connecting the plurality of first conductive plugs in parallel with the X direction, the bit line electrically connecting the plurality of diode cells by electrically connecting the plurality of first conductive plugs.
12. 12. The method of forming a memory structure as recited in claim 11, further comprising forming a plurality of word line extraction structures on said diode cell after forming said diode cell.
13. 13. The method of claim 1, further comprising forming an epitaxial layer on a surface of the substrate before doping the substrate to form a word line doped layer in the substrate, and doping the substrate on the word line doped layer to form a diode material layer on the word line doped layer.
14. 14. The method of claim 13, wherein doping the substrate on the word line doped layer to form a diode material layer on the word line doped layer further comprises doping the epitaxial layer.
15. 15. A memory structure formed by the method of forming a memory structure as claimed in any one of claims 1 to 14.

Description

Memory structure and forming method thereof Technical Field The present invention relates to semiconductor manufacturing processes, and more particularly, to a memory structure and a method of forming the same. Background The novel memory chip is subject to cross-talk as the process is scaled down. For this reason, transistor and resistive memory cell structures (1T 1R), diodes and resistive memory cell structures (1D 1R) have been developed to cope with this problem. The diode and Resistive Random Access Memory (RRAM) cell structure (1D 1R) has been attracting attention because of its simple structure, easy three-dimensional integration and high storage density. The cross-talk problem in resistive random access memories has been limiting their development as large-scale memories and has been exacerbated as the integration scale and density have increased. Because the diode area is smaller and the integration density is higher in the diode and resistance change memory unit structure (1D 1R), the problems of cross talk and substrate leakage current can be solved, and the deep trench isolation etching process is introduced to solve the problem of substrate leakage current by filling different insulating materials in multiple layers. However, the substrate leakage problem of the diode and resistive memory cell structures in the prior art is still further improved. Disclosure of Invention The invention provides a memory structure and a forming method thereof, wherein a second doping ion is injected into a substrate exposed by an isolation opening to form an isolation doping region, when the substrate is leaked, a reverse bias PN junction is formed between a word line doping layer and the substrate of the isolation doping region, so that the leakage current is cut off, the problem of substrate leakage is solved, an etching photomask with deep groove isolation is not needed, the process flow is simplified, the etching difficulty is reduced, in addition, higher density integration can be realized without great change, the control of more diode units can be realized by the word line doping layer, and the performance of the memory structure is improved. In order to solve the technical problems, the embodiment of the invention provides a method for forming a memory structure, which comprises the steps of providing a substrate, doping the substrate to form a word line doped layer in the substrate, doping the substrate on the word line doped layer or an epitaxial layer on the surface of the substrate to form a diode material layer on the word line doped layer, etching the substrate, the word line doped layer and the diode material layer to form a plurality of isolation openings, wherein the isolation openings expose the substrate of the isolation areas, doping the substrate exposed by the isolation openings to form an isolation doped region in the isolation area, and forming second doping ions in the isolation doped region, wherein the conductivity type of the first doping ions is opposite to that of the second doping ions. . Optionally, the conductivity type of the substrate comprises a P type, the conductivity type of the second doping ions comprises a P type, and the conductivity type of the substrate is the same as the conductivity type of the second doping ions. Optionally, the conductivity type of the substrate comprises an N type, the conductivity type of the second doping ions comprises an N type, and the conductivity type of the substrate is the same as the conductivity type of the second doping ions. Optionally, the ion doping concentration of the isolation doping region is greater than that of the substrate, the ion doping concentration of the second doping ion is in a range of 1E10atom/cm 2～1E15atom/cm2, and the ion doping concentration of the substrate is in a range of 1E10atom/cm 2～1E15atom/cm2. Optionally, the conductivity type of the first doping ions comprises a P type or an N type, and the conductivity type of the first doping ions is opposite to the conductivity type of the substrate. Optionally, the ion doping concentration range of the first doping ions is 1E10atom/cm 2～1E15atom/cm2. Optionally, the depth range of the isolation opening is: Optionally, the isolation opening forming method comprises the steps of forming a mask layer on the surface of the diode material layer, wherein the mask layer exposes part of the surface of the diode material layer, and etching the diode material layer, the word line doping layer and the substrate by taking the mask layer as a mask until the surface of the substrate is exposed, so that the isolation opening is formed. Optionally, the ion doping concentration of the word line doping layer is greater than the ion doping concentration of the diode material layer. Optionally, the active region and the isolation region are sequentially arranged along the X direction. Optionally, after the isolation doped region is formed, an isolation structure is formed in the isola