CN-122002814-A - Electronic chip comprising a memory circuit

Abstract

The present disclosure relates to electronic chips that include memory circuits. A memory circuit of a chip includes an interconnect stack and a number of memory cells, each memory cell including a memory element over the stack and a select transistor formed in a substrate and including a first node. Each element includes a first electrode, a layer formed of OTS material, and a second electrode connected to the layer on an opposite side relative to the first electrode. In each cell, the first node of the transistor is connected to the element via a conductive via extending through the entire thickness of the stack. The memory circuit further includes a control circuit configured to apply a first voltage pulse or a second voltage pulse having a first polarity or an opposite second polarity, respectively, between the first electrode and the second electrode of each element to set the first logic state or the second logic state of the element, respectively.

Inventors

• A. Lei Daili
• R. Anuzia Tower

Assignees

• 意法半导体国际公司

Dates

Publication Date

20260508

Application Date

20251107

Priority Date

20241107

Claims (17)

1. 1. An electronic chip comprising a memory circuit, comprising: A semiconductor substrate; An interconnect stack disposed on the semiconductor substrate, and A plurality of memory cells, wherein each memory cell comprises a memory element disposed over the interconnect stack and a select transistor formed in the semiconductor substrate and comprising a first conductive node; wherein each memory element comprises a first electrode, an intermediate layer comprising an ovonic threshold switching material, and a second electrode connected to the intermediate layer on an opposite side with respect to the first electrode; wherein in each memory cell a first conductive node of the select transistor is connected to the memory element via a respective conductive via extending through the entire thickness of the interconnect stack, and Wherein the memory circuit further comprises a control circuit constructed and arranged to apply a first voltage pulse of a first polarity between the first and second electrodes of each memory element to set a first logic state of the memory element, and to apply a second voltage pulse of a second polarity opposite to the first polarity between the first and second electrodes of each memory element to set a second logic state of the memory element.
2. 2. The electronic chip of claim 1, wherein the intermediate layer is made of a chalcogenide material, and wherein the second electrode comprises a resistor that electrically contacts the intermediate layer.
3. 3. The electronic chip of claim 1, wherein the memory cells are organized into an array of bit lines and word lines, and wherein each memory cell is connected to a respective bit line by its first electrode and to a respective word line by its second electrode.
4. 4. The electronic chip of claim 3, wherein each transistor includes a gate connected to a respective word line and a second conductive node connected to ground.
5. 5. The electronic chip of claim 1, wherein the memory cell is free of any phase change material.
6. 6. The electronic chip of claim 1, wherein said conductive via is made of a metallic material.
7. 7. The electronic chip of claim 1, wherein the interconnect stack has a thickness in a range from 100nm to 600 nm.
8. 8. The electronic chip of claim 1: Wherein the interconnect stack comprises a plurality of levels, each level comprising a first insulating layer and a second insulating layer, and Wherein the first insulating layer is made of a material selected from the group consisting of SiOC, porous SiOC, siOCH or porous SiOCH and has a thickness in the range from 30nm to 110nm, and Wherein the second insulating layer is made of a material selected from the group consisting of silicon carbonitride, silicon nitride, siCH, siNHC, or porous SiCN, and has a thickness in a range from 2nm to 50 nm.
9. 9. The electronic chip of claim 1, comprising: A third insulating layer interposed between the interconnect stack and the memory element, wherein the third insulating layer is made of a material selected from the group consisting of silicon carbonitride, silicon nitride, siCH, siNHC, or porous SiCN, and has a thickness in a range from 2nm to 50nm, and A fourth insulating layer interposed between the third insulating layer and the memory element, and wherein the fourth insulating layer is made of SiO 2 and has a thickness in a range from 10nm to 50 nm.
10. 10. The electronic chip of claim 1, wherein for each memory element, the respective conductive via is one-piece, forming a unitary, single conductive via body extending through an entire thickness of the interconnect stack.
11. 11. The electronic chip of claim 1, further comprising: an additional insulating layer interposed between the semiconductor substrate and the interconnect stack, and For each memory element, a respective further via extending through the entire thickness of the additional insulating layer and directly connecting the select transistor to the respective conductive via is also included.
12. 12. The electronic chip of claim 1, wherein the conductive via is directly connected to the second electrode of the memory element.
13. 13. The electronic chip of claim 1, wherein the select transistor is a fin field effect transistor.
14. 14. A method of manufacturing an electronic chip comprising a memory circuit, comprising the following successive steps: a) Forming a select transistor in a semiconductor substrate, the select transistor comprising a first conductive node; b) Forming an interconnect stack disposed on the semiconductor substrate, and C) Forming a plurality of memory elements arranged over the interconnect stack, each memory element comprising a first electrode, an intermediate layer comprising an ovonic threshold switching material, and a second electrode connected to the intermediate layer on an opposite side with respect to the first electrode; Wherein the first conductive node of the select transistor of each memory cell is connected to the memory element via a respective conductive via extending through the entire thickness of the interconnect stack, and D) Forming a control circuit constructed and arranged to apply a first voltage pulse of a first polarity between a first electrode and a second electrode of each memory element to set a first logic state of the memory element, and to apply a second voltage pulse of a second polarity opposite the first polarity between the first electrode and the second electrode of each memory element to set a second logic state of the memory element.
15. 15. The method of claim 14, further comprising forming the conductive via between steps b) and c).
16. 16. The method of claim 15, wherein forming the conductive via comprises: The interconnect stack is etched to form an opening extending therethrough, and the opening is filled with a metallic material.
17. 17. The method of claim 14, wherein the select transistor is a fin field effect transistor.

Description

Electronic chip comprising a memory circuit Priority claim The present application claims the benefit of priority from french patent application No. FR2412187 filed at 7 at 11 at 2024, the contents of which are incorporated herein by reference in their entirety to the maximum extent allowed by law. Technical Field The present description relates generally to electronic chips, and in particular, to electronic chips that include memory circuits based on ovonic threshold switching (ovonic threshold switching) (OTS) materials. Background The electronic chip includes both memory circuitry and logic circuitry. Of more particular interest are electronic chips that include memory circuits that include memory elements arranged in an array, each memory element being associated with one or more select transistors. The transistor is used to separately program, erase or read each memory element. An Ovonic Threshold Switching (OTS) material switches between an "on" state and an "off state depending on the amount of voltage potential applied across an electronic unit. When the voltage across the bidirectional threshold switch exceeds the threshold voltage, the state of the bidirectional threshold switch changes. Once the threshold voltage is reached, the "on" state is triggered and the bidirectional threshold switch is in a substantially on state. If the current or voltage potential drops below the threshold, the bi-directional threshold switch returns to the "off" state. It is desirable to at least partially improve some aspects of known electronic chips. Disclosure of Invention In an embodiment, an electronic chip comprising a memory circuit includes a semiconductor substrate, an interconnect stack disposed on the semiconductor substrate, and a plurality of memory cells, each memory cell including a memory element disposed over the interconnect stack and a select transistor including a first conductive node and formed in the semiconductor substrate, wherein each memory element includes a first electrode, an intermediate layer including an ovonic threshold switching material, and a second electrode connected to the intermediate layer on an opposite side with respect to the first electrode, wherein in each memory cell the first conductive node of the select transistor is connected to the memory element via a respective conductive via extending through an entire thickness of the interconnect stack, and wherein the memory circuit further includes a control circuit constructed and arranged to apply a first voltage pulse of a first polarity between the first electrode and the second electrode of each memory element to set a first logic state of the memory element, and to apply a second voltage pulse of a second polarity opposite to the first polarity between the first electrode and the second electrode of each memory element to set the second logic state of the memory element. According to an embodiment, the intermediate layer is made of chalcogenide material and the second electrode comprises a resistor, which is in electrical contact with the intermediate layer. According to an embodiment, the memory cells are organized into an array of bit lines and word lines, and each memory cell is connected to a respective bit line by its first electrode and to a respective word line by its second electrode. According to an embodiment, each transistor includes a gate connected to a respective word line and a second conductive node connected to ground. According to an embodiment, the memory cell does not contain any phase change material. According to an embodiment, the conductive via is made of a metallic material. According to an embodiment, the interconnect stack has a thickness in the range from 100nm to 600 nm. According to an embodiment, the interconnect stack comprises a plurality of levels, each level comprising a first insulating layer and a second insulating layer, the first insulating layer being made of a material selected from the group consisting of SiOC, porous SiOC, siOCH or porous SiOCH and having a thickness in the range from 30nm to 110nm, and the second insulating layer being made of a material selected from the group consisting of silicon carbonitride, silicon nitride, siCH, siNHC or porous SiCN and having a thickness in the range from 2nm to 50 nm. According to an embodiment, the electronic chip comprises a third insulating layer between the interconnect stack and the memory element, the third insulating layer being made of a material selected from the group consisting of silicon carbonitride, silicon nitride, siCH, siNHC or porous SiCN and having a thickness in the range from 2nm to 50nm, and a fourth insulating layer between the third insulating layer and the memory element, the fourth insulating layer being made of SiO 2 and having a thickness in the range from 10nm to 50 nm. According to an embodiment, for each memory element, the respective conductive via is one-piece. According to an embodiment, the electroni