CN-122002815-A - Synaptic memory unit for neuromorphic computation, preparation method and synaptic array

Abstract

The invention discloses a synaptic storage unit for nerve morphology calculation, a preparation method and a synaptic array, wherein the synaptic storage unit comprises two gating transistors and two resistance-changing memristors, the gating transistors are connected with the resistance-changing memristors in a one-to-one correspondence mode, each gating transistor comprises a grid electrode, a dielectric layer, a channel layer, a source electrode and a drain electrode which are sequentially arranged from bottom to top, the source electrode and the drain electrode are arranged on the surface of the channel layer, a first passivation layer is arranged between the source electrode and the drain electrode, the channel layer is made of hydrogenated amorphous silicon, the resistance-changing memristors comprise a bottom electrode, a resistance-changing layer and a top electrode which are sequentially arranged on the drain electrode, the resistance-changing layer is a hexagonal boron nitride film, and the two resistance-changing memristors are mutually connected through a metal layer arranged on the surface of the top electrode. The invention realizes low-temperature process compatibility, thereby being beneficial to three-dimensional stacking integration and obviously reducing the conductivity fluctuation coefficient.

Inventors

• ZHAO CHUN
• WU RUI

Assignees

• 苏州市华芯云睿微电子科技有限公司

Dates

Publication Date

20260508

Application Date

20260128

Claims (10)

1. 1. The synaptic storage unit for nerve morphology calculation is characterized by comprising two gating transistors and two resistance-changing memristors, wherein the gating transistors are connected with the resistance-changing memristors in a one-to-one correspondence manner; The gate transistor comprises a grid electrode, a dielectric layer, a channel layer, a source electrode and a drain electrode, wherein the grid electrode, the dielectric layer and the channel layer are sequentially arranged from bottom to top, and the source electrode and the drain electrode are arranged on the surface of the channel layer; The resistance change memristor comprises a bottom electrode, a resistance change layer, a top electrode and a second passivation layer, wherein the bottom electrode, the resistance change layer and the top electrode are sequentially arranged on the drain electrode, and the second passivation layer is arranged on the surface of the drain electrode and the surface of the first passivation layer; The two resistance-changing memristors are connected with each other through a metal layer arranged on the surface of the top electrode.
2. 2. The synaptic memory cell of claim 1, wherein an interfacial layer is further disposed between the bottom electrode and the resistive layer.
3. 3. The synaptic memory cell of claim 2, wherein the material of the interface layer is alumina.
4. 4. The synaptic memory cell of claim 1, wherein the dielectric layer has a thickness of 180-230 nm and the channel layer has a thickness of 30-80 nm.
5. 5. The synaptic memory cell of claim 1, wherein the resistive layer has a thickness of 5-15 nm and the bottom electrode and the top electrode each have a thickness of 30-70 nm.
6. 6. A method for preparing a synaptic memory unit according to any one of claims 1-5, comprising the steps of: The method comprises the steps of S1, preparing two gating transistors with the same structure, namely providing an insulating substrate, sequentially depositing a grid electrode, a dielectric layer and a channel layer on the surface of the insulating substrate, defining a channel region through a photoetching process, forming a channel structure after etching treatment, depositing a doped semiconductor layer on the channel structure, and patterning to form a source electrode and a drain electrode; S2, preparing two resistance-changing memristors with the same structure, wherein the preparation method specifically comprises the steps of sequentially depositing a bottom electrode, a resistance-changing layer and a top electrode on the surface of a drain electrode of the gating transistor; And step S3, connecting the two gating transistors with the resistance-changing memristor and performing passivation treatment to form a first passivation layer and a second passivation layer.
7. 7. The method according to claim 6, wherein in step S1, the channel layer is subjected to a hydrogenation treatment after the channel layer is prepared, and the hydrogenation treatment comprises annealing in a hydrogen plasma atmosphere.
8. 8. The method of claim 6, wherein in step S2, an interfacial layer is deposited on the bottom electrode surface by atomic layer deposition prior to depositing the resistive layer.
9. 9. The method according to claim 6, wherein in step S3, a metal layer is deposited on the top electrode surfaces of the two memristors, so that the top electrodes form an interconnection structure.
10. 10. A synaptic array for neuromorphic computation, comprising N x N synaptic storage cells according to any one of claims 1-5, wherein N is a positive integer, disposed on the same substrate.

Description

Synaptic memory unit for neuromorphic computation, preparation method and synaptic array Technical Field The invention relates to the technical field of neuromorphic computation, in particular to a synaptic storage unit for neuromorphic computation, a preparation method and a synaptic array. Background Neuromorphic hardware is a key direction in the field of artificial intelligence hardware, is currently limited to the inherent data handling bottleneck of von neumann architecture, is relatively difficult to break through in energy efficiency, and cannot meet the requirement of efficient computation. The 2T2R scheme of the mainstream double-transistor double-memristor generally depends on two-dimensional materials, the material transfer yield is low in practical application, a high-temperature environment exceeding 400 ℃ is needed in the process, three-dimensional stacking integration is greatly hindered, the improvement of storage and calculation density is limited, in addition, the conductivity fluctuation of the memristor is large, and the calculation precision is obviously restricted. The hexagonal boron nitride memristor has outstanding stability due to the excellent performance, but the current memristor of the type has not been effectively integrated with a transistor, and a differential weight programming function can not be achieved, so that the further application of the hexagonal boron nitride memristor in nerve morphology calculation is limited. Therefore, how to solve the defects and shortcomings of the prior art by an effective method has become an important problem to be solved by researchers in the field. Disclosure of Invention The object of the present invention is to address the above problems and to provide a synaptic storage unit, a method of manufacturing and a synaptic array for neuromorphic computation. The invention has the technical scheme that the synapse memory unit for nerve morphology calculation comprises two gating transistors and two resistance-changing memristors, wherein the gating transistors are connected with the resistance-changing memristors in a one-to-one correspondence manner; The gate transistor comprises a grid electrode, a dielectric layer, a channel layer, a source electrode and a drain electrode, wherein the grid electrode, the dielectric layer and the channel layer are sequentially arranged from bottom to top, and the source electrode and the drain electrode are arranged on the surface of the channel layer; The resistance change memristor comprises a bottom electrode, a resistance change layer, a top electrode and a second passivation layer, wherein the bottom electrode, the resistance change layer and the top electrode are sequentially arranged on the drain electrode, and the second passivation layer is arranged on the surface of the drain electrode and the surface of the first passivation layer; The two resistance-changing memristors are connected with each other through a metal layer arranged on the surface of the top electrode. As an improvement of the embodiment of the invention, an interface layer is also arranged between the bottom electrode and the resistive layer. As a modification of the embodiment of the present invention, the material of the interface layer is alumina. As an improvement of the embodiment of the invention, the thickness of the dielectric layer is 180-230 nm, and the thickness of the channel layer is 30-80 nm. As an improvement of the embodiment of the invention, the thickness of the resistance change layer is 5-15 nm, and the thicknesses of the bottom electrode and the top electrode are 30-70 nm. To achieve one of the above objects, an embodiment of the present invention provides a method for preparing a synaptic memory unit for neuromorphic computation, comprising the steps of: The method comprises the steps of S1, preparing two gating transistors with the same structure, namely providing an insulating substrate, sequentially depositing a grid electrode, a dielectric layer and a channel layer on the surface of the insulating substrate, defining a channel region through a photoetching process, forming a channel structure after etching treatment, depositing a doped semiconductor layer on the channel structure, and patterning to form a source electrode and a drain electrode; S2, preparing two resistance-changing memristors with the same structure, wherein the preparation method specifically comprises the steps of sequentially depositing a bottom electrode, a resistance-changing layer and a top electrode on the surface of a drain electrode of the gating transistor; And step S3, connecting the two gating transistors with the resistance-changing memristor and performing passivation treatment to form a first passivation layer and a second passivation layer. As an improvement of the embodiment of the present invention, in step S1, after the channel layer is prepared, the channel layer is subjected to a hydrogenation treatment, where the hy