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CN-122002816-A - Micro size structure for improving stability of device and forming method thereof

CN122002816ACN 122002816 ACN122002816 ACN 122002816ACN-122002816-A

Abstract

The application provides a miniature size structure for improving device stability and a forming method thereof. Belongs to the technical field of resistive random access memories. The method comprises the steps of preprocessing a substrate to generate a flat substrate surface structure of a characteristic structure, designing a sequentially laminated structure model of a lower metal interconnection layer/M n , a through hole, a lower electrode, a functional layer, an upper electrode and an upper metal interconnection layer/M n+1 according to the substrate surface structure, wherein the functional layer comprises a resistance change layer, a protective layer and an oxygen capture layer, a contact area of the resistance change layer structure and the lower electrode is arranged in the center of a lower electrode area, and the conductive filament can be accurately controlled to be generated in the center of a device through the design on the functional layer structure.

Inventors

  • KONG LINGBAO
  • CAI ZONGLIN
  • WANG ZHU
  • SU ZHIQIANG

Assignees

  • 钠存科技(杭州)有限公司

Dates

Publication Date
20260508
Application Date
20260212

Claims (9)

  1. 1. The miniature size structure for improving the stability of the device is characterized by comprising an upper metal interconnection layer/M n+1 (1), a dielectric layer and a lower metal interconnection layer/M n (10) which are sequentially stacked in the vertical direction, wherein a functional layer is arranged in the middle of the dielectric layer and is electrically connected with the upper metal interconnection layer/M n+1 (1) and the lower metal interconnection layer/M n (10).
  2. 2. The micro-scale structure for improving the stability of a device according to claim 1, wherein the lower part of the upper metal interconnection layer/M n+1 (1) is a downward protruding structure, and the protruding structure is in seamless connection with a concave structure above the upper electrode (3).
  3. 3. The miniature size structure for improving the stability of a device according to claim 2, wherein the dielectric layer is sequentially laminated with an upper electrode (3), a functional layer, a lower electrode (7) and a through hole (8) from top to bottom, and the functional layer is sequentially laminated with an oxygen capturing layer (6), a protective layer (4) and a resistive layer (5) from top to bottom.
  4. 4. The miniature size structure for improving the stability of a device according to claim 3, wherein the concave structure above the upper electrode (3) is the concave structure of the functional layer, the middle below the upper electrode (3) is a downward convex structure, and the structure is isosceles trapezoid.
  5. 5. The miniature size structure for improving the stability of a device according to claim 4, wherein the middle position above the upper electrode (3) is a multi-level inward concave structure, the structure is a multi-level isosceles trapezoid, and the concave structure is in seamless connection with the concave structure of the functional layer.
  6. 6. The miniature size structure for improving device stability according to claim 4, wherein the extension lines of two sides of isosceles trapezoid of the concave structure of the upper electrode (3) are parallel to the sides of the protective layer (4), the resistive layer (5) and the oxygen capturing layer (6) in the vertical direction, respectively.
  7. 7. The micro-scale structure for improving device stability according to claim 4, wherein the upper and lower bottoms of the lower electrode (7) are parallel to the sides of the protective layer (4), the resistive layer (5) and the oxygen capturing layer (6) in the vertical direction, respectively.
  8. 8. A micro-scale structure for improving device stability according to claim 3, wherein the through hole (8) is an isosceles trapezoid structure, and the length of the upper bottom of the isosceles trapezoid structure is larger than that of the lower bottom, the upper bottom is connected with the lower bottom of the lower electrode (7), and the lower bottom is located on the lower metal interconnection layer/M n (10).
  9. 9. A method for forming a miniature size structure for improving device stability as claimed in claim 1, said method comprising: Forming a lower metal interconnection layer/M n on a semiconductor substrate, performing surface planarization treatment to generate a basic electrode interconnection plane, and performing deposition of a dielectric layer B according to the basic electrode interconnection plane to generate an initial dielectric structure; Performing inverse trapezoid through hole patterning treatment according to the initial medium structure, filling conductive materials in the inverse trapezoid through holes to generate lower electrode constraint area through holes, performing conformal deposition and planarization treatment on the lower electrode materials and the medium layer A through the lower electrode constraint area through holes to generate a composite medium structure with an exposed window preparation surface; performing accurate photoetching and etching treatment according to the exposed window preparation surface of the composite medium structure to generate a graphical window with a preset inclination angle on the side wall and a part of the lower electrode surface exposed at the bottom, accurately controlling the effective contact area between a subsequent functional layer and the lower electrode through the geometric dimension of the graphical window, and generating a functional layer deposition foundation with controllable contact area; According to the deposition foundation of the functional layer with controllable contact area, adopting a conformal deposition process in the graphical window, and sequentially depositing a resistive layer, a protective layer, an oxygen capture layer and an upper electrode material from bottom to top to generate an embedded functional laminated structure and an upper electrode, wherein the embedded functional laminated structure and the upper electrode guide conductive filaments to form in a preset central area through the geometric shape and the material characteristics of the embedded functional laminated structure and the upper electrode; And performing patterning treatment of the upper metal interconnection layer/M n+1 according to the device isolation structure, and forming electrical connection with the upper electrode, thereby finally completing the integrated manufacture of the structure capable of improving the stability of the device by reducing the size.

Description

Micro size structure for improving stability of device and forming method thereof Technical Field The invention provides a miniature size structure for improving device stability and a forming method thereof, and belongs to the technical field of resistive random access memories. Background In the field of modern electronics, memory is used as a core component for data storage and processing, and its performance and stability are directly related to the operation efficiency and reliability of the whole electronic system. With the rapid development of the emerging technologies such as the internet of things, artificial intelligence and big data, higher requirements are put forward on a memory, so that the memory is required to have the characteristics of high density, low power consumption, rapid reading and writing and the like, and stable performance is required to be kept in an extreme environment. Resistive random access memory (RRAM, RESISTIVE RANDOM ACCESS MEMORY) has received attention as a nonvolatile memory based on the principle of resistance change because of its unique advantages. The RRAM realizes reversible switching between a high-resistance state and a low-resistance state by regulating and controlling the formation and fracture of conductive filaments in a dielectric layer (such as HfO 2、TaOx and the like) through an electric field, so that data storage and reading are completed. Compared with the traditional Flash memory and Dynamic Random Access Memory (DRAM), the RRAM has the remarkable advantages of simple structure, low operation voltage (generally less than 3V), high speed (nanosecond switching), high durability (more than 1012 cycles) and the like, and has the potential of breaking through 5nm node miniaturization, so that the RRAM has wide application prospect in high-density storage and memory integrated chips and Internet of things equipment. However, despite the advantages of RRAM technology, its commercial application still faces many challenges. Among them, the randomness of the conductive filament formation is a key problem, which leads to large fluctuation of device parameters, affecting the consistency and reliability of operation. In particular, random aggregation of oxygen vacancies or metal ions can lead to fluctuations in Set/Reset voltage, which can be as high as σ/Vset20%, severely limiting the performance of RRAM devices in large scale integration and commercial applications. In addition, as device dimensions shrink, the operating voltage tends to increase, further limiting the scaling potential and energy efficiency ratio of the RRAM. In addition to the randomness problem of conductive filament formation, the resistive state drift induced by oxygen vacancy migration is also an important factor limiting RRAM reliability and durability. In long-term use or extreme environments, migration of oxygen vacancies may cause changes in the resistance state, thereby affecting stable storage of data. At the same time, the atomic-level mechanisms of conductive filament dynamic behavior are still not well known, which limits the possibilities for further device performance enhancement through material selection and process optimization. At present, although some researches have been attempted to overcome the above-mentioned challenges by improving the structure or material of the RRAM, for example, using a ring-shaped bottom electrode structure to guide the growth direction of the conductive filaments, these schemes often have limitations such as failure to achieve the central formation of the conductive filaments, the resistance change layer being affected by plasma (plasma) to cause the material characteristics to be denatured, and so on. Therefore, developing a new RRAM structure capable of shrinking the size while improving the stability of the device is an important direction of current research. Disclosure of Invention The present invention provides a micro-size structure for improving the stability of a device and a forming method thereof, which are used for solving the problems mentioned in the background art: The invention provides a miniature size structure for improving device stability, which comprises an upper metal interconnection layer/M n+1, a dielectric layer and a lower metal interconnection layer/M n which are sequentially stacked in the vertical direction, wherein a functional layer is arranged in the middle of the dielectric layer and is electrically connected with the upper metal interconnection layer/M n+1 and the lower metal interconnection layer/M n. Optionally, a downward protruding structure is disposed below the upper metal interconnection layer/M n+1, and the protruding structure is in seamless connection with a concave structure above the upper electrode. Optionally, the dielectric layer is laminated with upper electrode, functional layer, bottom electrode and through-hole from top to bottom in proper order, the functional layer is laminated with oxyge