CN-122002817-A - High bandwidth memory stack with side interconnect and three dimensional integrated circuit structure with the same

Abstract

An integrated circuit structure includes a memory stack having semiconductor wafers horizontally separated from one another, wherein each semiconductor wafer has a top surface, a bottom surface, four sidewalls, and a plurality of edge pads disposed along the sidewalls. The integrated circuit structure further includes a memory controller located below the first memory stack and electrically connected to the edge pads of each semiconductor die, a processor circuit located above and electrically connected to the memory controller, and a package substrate located below and electrically connected to the memory controller. The die area of the memory controller is greater than the sum of the horizontal cross-sectional area of the memory stack and the die area of the processor circuit. There is no interposer between the package substrate and the memory controller, and no through silicon vias in each semiconductor die.

Inventors

• TANG HEMING
• LU CHAOQUN

Assignees

• 铨心半导体异质整合股份有限公司
• 钰创科技股份有限公司

Dates

Publication Date

20260508

Application Date

20251013

Priority Date

20250221

Claims (20)

1. 1. An integrated circuit structure, comprising: A first memory stack, comprising: A plurality of semiconductor wafers horizontally separated from each other, wherein each of the semiconductor wafers comprises a top surface, a bottom surface opposite to the top surface, and four side walls including a first side wall, a second side wall, a third side wall, and a fourth side wall, and a plurality of edge pads arranged along the first side wall, wherein the area of the bottom surface or the top surface of each of the semiconductor wafers is larger than the area of either side wall, and A logic die having a memory controller underlying the first memory stack and electrically connected to the plurality of edge pads of each of the semiconductor dies; A logic chip with a processor circuit, which is located above and electrically connected with the logic chip with a memory controller, and A package substrate under the logic chip with a memory controller and electrically connected with the logic chip, Wherein the die area of the logic die having a memory controller is greater than the sum of the horizontal cross-sectional area of the first memory stack and the die area of the logic die having a processor circuit, Wherein no interposer is present between the package substrate and the logic die with memory controller and no through silicon vias are present in each of the semiconductor die.
2. 2. The integrated circuit structure of claim 1, further comprising: An upwardly extending thermally conductive layer located between two adjacent semiconductor chips, wherein the upwardly extending thermally conductive layer has a thermal conductivity higher than that of silicon or silicon dioxide, and/or A laterally extending thermally conductive layer covering each of the second sidewalls of the plurality of semiconductor chips and thermally coupled to the upwardly extending thermally conductive layer, wherein the laterally extending thermally conductive layer is opposite the first sidewalls of the plurality of semiconductor chips and the laterally extending thermally conductive layer has a thermal conductivity higher than a thermal conductivity of silicon or silicon dioxide.
3. 3. The integrated circuit structure of claim 2, wherein the upwardly extending thermally conductive layer or the laterally extending thermally conductive layer comprises undoped polysilicon, large scale crystalline silicon, silicon carbide, boron nitride, aluminum nitride, tungsten, or copper.
4. 4. The integrated circuit structure of claim 1, wherein each of the semiconductor dies comprises a dynamic random access memory die, and the plurality of edge pads of each of the dynamic random access memory dies comprises about 128 to 5000 edge pads, and a spacing between two adjacent ones of the edge pads is between about 5 μm and about 100 μm.
5. 5. The integrated circuit structure of claim 4, wherein the plurality of edge pads of each of the semiconductor dies comprise a subset of data pads, and the logic die with memory controller selects a predetermined data width from a subset of data pads of a portion of one of the semiconductor dies or the plurality of semiconductor dies or all of the plurality of semiconductor dies.
6. 6. The integrated circuit structure of claim 5, wherein the predetermined data width selected by the logic die having a memory controller is set by a mode register in each of the semiconductor die.
7. 7. The integrated circuit structure of claim 5, wherein the logic die having a memory controller selects the predetermined data width from a subset of data pads of a portion or all of the plurality of semiconductor die through a cross-over circuit.
8. 8. The integrated circuit structure of claim 5, wherein: The logic chip with memory controller selects the predetermined data width from a subset of the data pads of one, a portion of the plurality of semiconductor chips or all of the plurality of semiconductor chips through a plurality of static random access memory arrays respectively corresponding to the plurality of semiconductor chips, Wherein each of the SRAM arrays temporarily stores a predetermined data width from the corresponding semiconductor die.
9. 9. The integrated circuit structure of claim 4, wherein the logic die having a memory controller comprises a plurality of through silicon vias.
10. 10. The integrated circuit structure of claim 1, further comprising a heat spreader located over the logic die with processor circuitry, and a top surface of the heat spreader is flush with a top surface of the first memory stack.
11. 11. The integrated circuit structure of claim 1, further comprising: A second memory stack, comprising: A plurality of semiconductor chips horizontally separated from each other, wherein each of the semiconductor chips comprises a top surface, a bottom surface opposite to the top surface, and four side walls having a first side wall, a second side wall, a third side wall, and a fourth side wall, and a plurality of edge pads arranged along the first side wall, wherein the area of the bottom surface or the top surface of each of the semiconductor chips of the second memory stack is larger than the area of either side wall, and An upwardly extending thermally conductive layer located between two adjacent ones of the semiconductor chips, wherein the upwardly extending thermally conductive layer has a thermal conductivity higher than a thermal conductivity of silicon or silicon dioxide, Wherein the first memory stack and the second memory stack are horizontally spaced apart from the logic die with processor circuitry and disposed along a side of the logic die with processor circuitry.
12. 12. The integrated circuit structure of claim 1, further comprising: A second memory stack, a third memory stack, and a fourth memory stack, each comprising: A plurality of semiconductor chips horizontally separated from each other, wherein each of the semiconductor chips comprises a top surface, a bottom surface opposite to the top surface, and four side walls having a first side wall, a second side wall, a third side wall, and a fourth side wall, and a plurality of edge pads arranged along the first side wall, wherein the area of the bottom surface or the top surface is larger than the area of either side wall, and An upwardly extending thermally conductive layer located between two adjacent ones of the semiconductor chips, wherein the upwardly extending thermally conductive layer has a thermal conductivity higher than a thermal conductivity of silicon or silicon dioxide, Wherein the first memory stack, the second memory stack, the third memory stack, and the fourth memory stack are horizontally spaced apart from the logic die with processor circuitry and are disposed along four sides of the logic die with processor circuitry, respectively.
13. 13. The integrated circuit structure of claim 1, wherein each of the edge pads of each of the semiconductor chips comprises an edge contact in a back end of line (BEOL) and a conductive via in a dielectric layer above the edge contact and at the top surface, wherein an area of the conductive via is greater than an area of the edge contact.
14. 14. The integrated circuit structure of claim 1, wherein each of the edge pads of each of the semiconductor die comprises an edge contact in a back end of line region and a conductive via in a redistribution layer RDL above the edge contact and at the top surface, wherein an area of the conductive via is greater than an area of the edge contact.
15. 15. The integrated circuit structure of claim 14, wherein the edge contact is electrically connected to a signal pad in a back-end-of-line region of the semiconductor die, the signal pad being surrounded by a seal ring structure.
16. 16. The integrated circuit structure of claim 1, wherein each of the edge pads of each of the semiconductor die comprises a wire in a redistribution layer RDL that is electrically connected to a signal pad in a back end of line region of the semiconductor die, the signal pad being surrounded by a seal ring structure.
17. 17. The integrated circuit structure of claim 16, wherein the RDL comprises a plurality of stacked dielectric layers and the wire is located therein.
18. 18. The integrated circuit structure of claim 17, wherein a portion of the wire is configured to be positioned in a scribe line region of a semiconductor wafer prior to dicing the semiconductor wafer.
19. 19. An integrated circuit structure, comprising: a memory stack, comprising: A plurality of semiconductor wafers horizontally separated from each other, wherein each of the semiconductor wafers comprises a top surface, a bottom surface opposite to the top surface, and four side walls having a first side wall, a second side wall, a third side wall, and a fourth side wall, and a plurality of edge pads disposed along the first side wall, wherein the area of the bottom surface or the top surface of each of the semiconductor wafers is larger than the area of either side wall, and A logic die having a memory controller and a processor circuit underlying the memory stack and electrically connected to the plurality of edge pads of each of the semiconductor dies, and The packaging substrate is positioned below the logic chip with the memory controller and the processor and is electrically connected with the logic chip; Wherein no interposer is present between the package substrate and the logic die having memory controller and processor circuitry, and no through silicon vias are present in each of the semiconductor die.
20. 20. The integrated circuit structure of claim 19, further comprising: An upwardly extending thermally conductive layer located between two adjacent semiconductor chips, wherein the upwardly extending thermally conductive layer has a thermal conductivity higher than that of silicon or silicon dioxide, and/or A laterally extending thermally conductive layer covering each of the second sidewalls of the plurality of semiconductor chips and thermally coupled to the upwardly extending thermally conductive layer, wherein the laterally extending thermally conductive layer is opposite the first sidewalls of the plurality of semiconductor chips and the laterally extending thermally conductive layer has a thermal conductivity higher than a thermal conductivity of silicon or silicon dioxide.

Description

High bandwidth memory stack with side interconnect and three dimensional integrated circuit structure with the same Technical Field The present disclosure relates generally to memory stacks within Integrated Circuit (IC) structures, and more particularly to a high bandwidth memory stack with side interconnect and a three-dimensional (3D) IC structure including the same. Background 2.5D/3D ICs have been recognized as next generation semiconductor technology, which has the advantages of high performance, low power consumption, small physical size, and high integration density. 2.5D/3D ICs provide a way to continuously meet the performance and cost requirements of next generation devices while still allowing for more relaxed gate lengths and lower process complexity. Thus, 2.5D/3D ICs are expected to find wide applicability in applications such as High Performance Computing (HPC) and data centers, artificial Intelligence (AI)/Machine Learning (ML), 5G/6G networks, graphics, smart phones/wearable devices, automobiles, and other applications requiring "extreme", ultra-high performance, higher power devices. Commercial 2.5D/3D ICs, such as 3D High Bandwidth Memory (HBM) logically DRAM memory die stacks, are increasingly being reused, with the HBM devices containing Through Silicon Vias (TSVs) in the active die and silicon interposer. In addition, 2.5D/3D ICs also allow heterogeneous vertical stacking of wafers from different processes and nodes, wafer reuse, and small-sized wafer in SiP (system in package) for high performance applications that have broken through the limit of single-chip at the most advanced nodes. As shown in fig. 1, the on-substrate wafer (COWOS) structure 20 includes an HBM structure 21 with TSVs 201 (with multiple DRAM memory dies 211 and controllers 213), a logic die 22 (e.g., GPU or SOC die), a silicon interposer 23 with TSVs, and a package substrate 24, where the HBM structure 21 and logic die 22 are stacked on the silicon interposer 23, followed by the silicon interposer 23 being stacked on the package substrate 24. However, 2.5D/3D ICs employ a packaging topology with bottom/top electrical interconnects that result from the interconnect technology described above, such as micro bumps, TSVs, and redistribution layers (RDLs). The bottom/top electrical interconnects impose severe limitations on the power, performance, area, and cost (PPAC) optimization of 3D IC designers when proposing optimal design solutions, particularly the difficulty of forming TSVs in semiconductor wafers and the alignment of TSVs per semiconductor wafer. In addition, as silicon wafers have grown rapidly from GSI (billions of transistors on a wafer) to TSI (mega-scale: several mega-transistors on a wafer), the power consumption of operating such large numbers of transistors increases dramatically, which disadvantageously increases the junction temperature of the transistors and increases the temperature of the entire wafer due to the current limited heat dissipation capability (e.g., very low silicon dioxide/silicon thermal conductivity index). Furthermore, since a plurality of DRAM memory semiconductor chips (or HBMs) are stacked in a 2.5D/3D IC, the problem of insufficient heat dissipation leads to an increase in the chip operating temperature, which is considered to be the most serious problem of the HBM structure. Disclosure of Invention According to a first aspect of the present disclosure, an IC structure includes a first memory stack having a plurality of semiconductor wafers horizontally separated from one another, wherein each of the semiconductor wafers includes a top surface, a bottom surface opposite the top surface, and four sidewalls having first, second, third, and fourth sidewalls, and a plurality of edge pads disposed along the first sidewalls. The area of the bottom surface or the top surface of each semiconductor wafer is larger than the area of either sidewall. The IC structure further includes a logic die having a memory controller located below the first memory stack and electrically connected to the plurality of edge pads of each semiconductor die, a logic die having a processor circuit located above and electrically connected to the logic die having a memory controller, and a package substrate located below and electrically connected to the logic die having a memory controller. The die area of the logic die having a memory controller is greater than a sum of the horizontal cross-sectional area of the first memory stack and the die area of the logic die having a processor circuit. There is no interposer between the package substrate and the logic die with memory controller, and no TSV is present in each of the semiconductor die. According to some embodiments of the present disclosure, the IC structure further includes an upwardly extending thermally conductive layer and/or a laterally extending thermally conductive layer. The upwardly extending thermally conductive layer is located between two