CN-122002818-A - Wafer-on-substrate integrated circuit structure with edge pad semiconductor die

Abstract

An integrated circuit structure includes a memory stack including a plurality of semiconductor dies, a memory control die, an interposer, a logic processor die, and a package substrate that are horizontally separated from one another. Each semiconductor wafer includes a top surface, a bottom surface, four sidewalls, and a plurality of edge pads disposed along the first sidewalls. The memory control wafer is disposed below and electrically connected to the plurality of edge pads of each semiconductor wafer, wherein the first sidewall of each semiconductor wafer faces the memory control wafer. The interposer is disposed under and electrically connected to the memory control chip. The logic processor die is electrically connected to the memory control die. The package substrate is disposed under and electrically connected to the interposer.

Inventors

• TANG HEMING
• LU CHAOQUN

Assignees

• 铨心半导体异质整合股份有限公司
• 钰创科技股份有限公司

Dates

Publication Date

20260508

Application Date

20251014

Priority Date

20250221

Claims (12)

1. 1. An integrated circuit structure, comprising: a memory stack, comprising: A plurality of semiconductor wafers horizontally separated from each other, wherein each of the semiconductor wafers comprises a top surface, a bottom surface opposite to the top surface, and four sidewalls including a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall, and a plurality of edge pads disposed along the first sidewall, wherein an area of the bottom surface or the top surface of each of the semiconductor wafers is larger than an area of either sidewall; a memory control chip located under and electrically connected to the plurality of edge pads of each of the semiconductor chips, wherein the first sidewall of each of the semiconductor chips faces the memory control chip; an interposer under the memory control chip and electrically connected with the memory control chip; A logic processor chip electrically connected to the memory control chip, and And the packaging substrate is positioned below the medium layer and is electrically connected with the medium layer.
2. 2. The integrated circuit structure of claim 1, the memory stack further comprising: a laterally extending thermally conductive layer covering each of the second sidewalls of the plurality of semiconductor chips, and/or An upwardly extending thermally conductive layer attached to the top surface or the bottom surface of the first semiconductor wafer, Wherein the laterally extending thermally conductive layer or the upwardly extending thermally conductive layer has a thermal conductivity higher than that of silicon or silicon dioxide.
3. 3. The integrated circuit structure of claim 2, wherein the upwardly extending thermally conductive layer is thermally coupled to the laterally extending thermally conductive layer, and the upwardly extending thermally conductive layer or the laterally extending thermally conductive layer comprises silicon carbide, boron nitride, aluminum nitride, tungsten, or copper.
4. 4. The integrated circuit structure of claim 2, the upwardly extending thermally conductive layer disposed between the first semiconductor die and the second semiconductor die, or the upwardly extending thermally conductive layer is located on an outermost sidewall of the memory stack.
5. 5. The integrated circuit structure of claim 1, wherein each of the semiconductor dies is a dynamic random access memory die and includes a data output between 128 and 2048 bits.
6. 6. The integrated circuit structure of claim 1, wherein each of the edge pads of each of the semiconductor chips comprises: Edge contacts in the back end of line BEOL and Conductive vias over the edge contacts and in the dielectric layer or redistribution layer RDL, wherein the conductive vias have an area greater than the area of the edge contacts.
7. 7. The integrated circuit structure of claim 6, wherein the edge contact is electrically connected to a signal pad in a back-end-of-line region of the semiconductor die, the signal pad being surrounded by a seal ring structure.
8. 8. The integrated circuit structure of claim 1, wherein each of the edge pads of each of the semiconductor die comprises a wire in a redistribution layer RDL that is electrically connected to a signal pad in a back end of line region of the semiconductor die, the signal pad being surrounded by a seal ring structure.
9. 9. The integrated circuit structure of claim 8, wherein the RDL comprises a plurality of stacked dielectric layers and the wire is located therein.
10. 10. The integrated circuit structure of claim 9, wherein a portion of the wire is configured to be disposed in scribe line region SL of the semiconductor wafer prior to dicing of the semiconductor wafer.
11. 11. The integrated circuit structure of claim 1, wherein the logic processor die is disposed over the interposer and a heat spreader is disposed over the logic processor die, wherein a top surface of the heat spreader is substantially flush with a top surface of the memory stack.
12. 12. The integrated circuit structure of claim 1, wherein the memory stack further comprises an upwardly extending thermally conductive layer covering each of the third sidewalls of the plurality of semiconductor chips, wherein the upwardly extending thermally conductive layer is thermally coupled to the laterally extending thermally conductive layer over each of the second sidewalls of the plurality of semiconductor chips, and the upwardly extending thermally conductive layer has a thermal conductivity higher than a thermal conductivity of silicon or silicon dioxide.

Description

Wafer-on-substrate integrated circuit structure with edge pad semiconductor die Technical Field The present disclosure relates generally to a wafer-on-substrate (COWOS) Integrated Circuit (IC) structure, and more particularly to a COWOS IC structure with edge-pad semiconductor die. Background 2.5D/3D ICs have been recognized as next generation semiconductor technology, which has the advantages of high performance, low power consumption, small physical size, and high integration density. 2.5D/3D ICs provide a way to continuously meet the performance and cost requirements of next generation devices while still allowing for more relaxed gate lengths and lower process complexity. Thus, 2.5D/3D ICs are expected to find wide applicability in applications such as High Performance Computing (HPC) and data centers, artificial Intelligence (AI)/Machine Learning (ML), 5G/6G networks, graphics, smart phones/wearable devices, automobiles, and other applications requiring "extreme", ultra-high performance, higher power devices. Commercial 2.5D/3D ICs, such as 3D High Bandwidth Memory (HBM) logically DRAM memory die stacks, are increasingly being reused, with the HBM devices containing Through Silicon Vias (TSVs) in the active die and silicon interposer. In addition, 2.5D/3D ICs also allow heterogeneous vertical stacking of wafers from different processes and nodes, wafer reuse, and small-sized wafer in SiP (system in package) for high performance applications that have broken through the limit of single-chip at the most advanced nodes. As shown in fig. 1, the on-substrate wafer (COWOS) structure 20 includes an HBM structure 21 with TSVs 201 (with multiple DRAM memory dies 211 and controls 213), a logic die 22 (e.g., GPU or SOC die), a silicon interposer 23 with TSVs, and a package substrate 24, where the HBM structure 21 and logic die 22 are stacked on the silicon interposer 23, followed by the silicon interposer 23 being stacked on the package substrate 24. However, 2.5D/3D ICs employ a packaging topology with bottom/top electrical interconnects that result from the interconnect technology described above, such as micro bumps, TSVs, and redistribution layers (RDLs). The bottom/top electrical interconnects impose severe limitations on the power, performance, area, and cost (PPAC) optimization of 3D IC designers when proposing optimal design solutions, particularly the difficulty of forming TSVs in semiconductor wafers and the alignment of TSVs per semiconductor wafer. In addition, as silicon wafers have grown rapidly from GSI (billions of transistors on a wafer) to TSI (mega-scale: several mega-transistors on a wafer), the power consumption of operating such large numbers of transistors increases dramatically, which disadvantageously increases the junction temperature of the transistors and increases the temperature of the entire wafer due to the current limited heat dissipation capability (e.g., very low silicon dioxide/silicon thermal conductivity index). Furthermore, since a plurality of DRAM memory semiconductor chips (or HBMs) are stacked in a 2.5D/3D IC, the problem of insufficient heat dissipation leads to an increase in the chip operating temperature, which is considered to be the most serious problem of the HBM structure. Disclosure of Invention According to a first aspect of the present disclosure, an IC structure includes a memory stack, a memory control die, an interposer, a logic processor die, and a package substrate. The memory stack includes a plurality of semiconductor dies. The plurality of semiconductor wafers are horizontally separated from one another, wherein each of the semiconductor wafers includes a top surface, a bottom surface opposite the top surface, and four sidewalls including a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall, and a plurality of edge pads disposed along the first sidewall, wherein an area of the bottom surface or the top surface of each of the semiconductor wafers is greater than an area of either sidewall. The memory control die is disposed below and electrically connected to the plurality of edge pads of each semiconductor die, wherein the first sidewall of each semiconductor die faces the memory control die. The interposer is disposed below and electrically connected to the memory control chip. The logic processor die is electrically connected to the memory control die. The package substrate is disposed below and electrically connected to the interposer. According to some embodiments of the present disclosure, the memory stack further includes an upwardly extending thermally conductive layer and/or a laterally extending thermally conductive layer. The laterally extending thermally conductive layer covers each of the second sidewalls of the plurality of semiconductor wafers. The upwardly extending thermally conductive layer is attached to the top surface or the bottom surface of the first semiconductor wafer, wherein the laterally extending ther