CN-122002819-A - Semiconductor package

Abstract

A semiconductor package is provided. The semiconductor package includes a base chip, a plurality of first semiconductor chips stacked on the base chip, a dummy chip stacked on an uppermost first semiconductor chip of the plurality of first semiconductor chips, and a molding structure surrounding the base chip, the plurality of first semiconductor chips, and the dummy chip, wherein the dummy chip includes a channel extending from an upper surface of the dummy chip to a lower surface of the dummy chip, the channel having a shape extending from a center of the dummy chip to at least any one point located at an edge of the dummy chip in a horizontal direction in a top view, and the molding structure filling the channel.

Inventors

• LI XIANMIN
• Shen Hengche

Assignees

• 三星电子株式会社

Dates

Publication Date

20260508

Application Date

20251029

Priority Date

20241105

Claims (20)

1. 1. A semiconductor package, comprising: a base chip; A plurality of first semiconductor chips on the base chip; A dummy chip on an uppermost first semiconductor chip of the plurality of first semiconductor chips, and A molding structure surrounding the plurality of first semiconductor chips and the dummy chip on the base chip, Wherein the dummy chip includes a channel extending from an upper surface of the dummy chip to a lower surface of the dummy chip in a first direction, the channel extending from a center of the dummy chip to an edge of the dummy chip in a second direction perpendicular to the first direction, and Wherein the molded structure is disposed at the channel.
2. 2. The semiconductor package of claim 1, wherein the channel comprises: A first portion having an X-shape in a plane perpendicular to the first direction, the first portion extending from a center of the dummy chip to four vertices of the dummy chip, and A second portion having a rectangular ring shape in the plane, the second portion being partially overlapped with the first portion.
3. 3. The semiconductor package of claim 1, wherein the channel comprises: A first portion having a plus sign shape in a plane perpendicular to the first direction, the first portion extending from a center of the dummy chip to a center of four sides of the dummy chip, and A second portion having a rectangular ring shape in the plane, the second portion being partially overlapped with the first portion.
4. 4. The semiconductor package of claim 1, wherein the channel comprises: A first portion having an X-shape in a plane perpendicular to the first direction, the first portion extending from a center of the dummy chip to four vertices of the dummy chip; a second portion having a plus sign shape in the plane, the second portion extending from a center of the dummy chip to a center of four sides of the dummy chip, and And a third portion having a rectangular ring shape in the plane.
5. 5. The semiconductor package according to claim 1, wherein the channel comprises a first component and a second component stacked along a first direction, and Wherein a width of the first part of the channel along the second direction is different from a width of the second part of the channel along the second direction.
6. 6. The semiconductor package according to claim 5, wherein a cross section of the channel in a plane parallel to the first direction has a trapezoidal shape, and Wherein the width of the channel along the second direction gradually decreases toward the uppermost first semiconductor chip.
7. 7. The semiconductor package of claim 1, wherein a volume of the molded structure disposed at the channel is in a range of 1% to 3% of a total volume of the dummy chip.
8. 8. The semiconductor package of claim 1, wherein an upper surface of the molded structure disposed at the channel is coplanar with an upper surface of the dummy chip.
9. 9. The semiconductor package of claim 1, wherein the dummy chip is insulated from an uppermost first semiconductor chip.
10. 10. The semiconductor package of any one of claims 1 to 9, wherein the plurality of first semiconductor chips have no bumps between adjacent ones of the plurality of first semiconductor chips.
11. 11. A semiconductor package, comprising: a base chip; A plurality of first semiconductor chips on the base chip along a first direction, and A dummy chip on an uppermost first semiconductor chip of the plurality of first semiconductor chips, the dummy chip having a channel extending upward from a lower surface of the dummy chip, Wherein the channel extends from the center of the dummy chip to at least four points located at the edges of the dummy chip, Wherein the plurality of first semiconductor chips are stacked by direct bonding, and Wherein the dummy chip is insulated from the uppermost first semiconductor chip.
12. 12. The semiconductor package according to claim 11, wherein the channel extends in the first direction from a lower surface of the dummy chip to an upper surface of the dummy chip, Wherein the trench includes a first member and a second member arranged on the first member along a first direction, the first member being between the second member and an uppermost first semiconductor chip along the first direction, and Wherein the width of the first member along a second direction perpendicular to the first direction is constant, and the width of the second member along the second direction gradually increases toward the upper surface of the dummy chip.
13. 13. The semiconductor package according to claim 11, wherein the channel extends in the first direction from a lower surface of the dummy chip to an upper surface of the dummy chip, Wherein the cross section of the channel in a plane parallel to the first direction has a trapezoidal shape, an Wherein the width of the channel along the second direction is gradually reduced from the upper surface of the dummy chip toward the lower surface of the dummy chip, the second direction being perpendicular to the first direction.
14. 14. The semiconductor package of any of claims 11-13, wherein the channel comprises: A first portion having an X-shape in a plane perpendicular to the first direction, the first portion extending from a center of the dummy chip to four vertices of the dummy chip, and A second portion having a rectangular ring shape in the plane, the second portion being partially overlapped with the first portion.
15. 15. The semiconductor package of any of claims 11-13, wherein the channel comprises: A first portion having a plus sign shape in a plane perpendicular to the first direction, the first portion extending from a center of the dummy chip to a center of four sides of the dummy chip, and A second portion having a rectangular ring shape in the plane, the second portion being partially overlapped with the first portion.
16. 16. The semiconductor package of any of claims 11-13, wherein the channel comprises: A first portion having an X-shape in a plane perpendicular to the first direction, the first portion extending from a center of the dummy chip to four vertices of the dummy chip, and A second portion having a plus sign shape in the plane, the second portion extending from a center of the dummy chip to a center of four sides of the dummy chip, and And a third portion having a rectangular ring shape in the plane.
17. 17. A semiconductor package, comprising: a first substrate; A base chip on the first substrate along a first direction; a plurality of first semiconductor chips stacked on the base chip along a first direction; A dummy chip on an uppermost first semiconductor chip of the plurality of first semiconductor chips, the dummy chip having a channel extending from a lower surface of the dummy chip to an upper surface of the dummy chip along a first direction; a first molding structure surrounding the plurality of first semiconductor chips and the dummy chip on the base chip, the first molding structure filling the trench, and A second molded structure on the first substrate surrounding a side surface of the first molded structure and a side surface of the base chip, Wherein the semiconductor die pad and a dielectric layer surrounding a side surface of the semiconductor die pad are on each of a lower surface and an upper surface of the plurality of first semiconductor dies, Wherein the channel extends from the center of the dummy chip to at least four points located at the edge of the dummy chip in a first plane perpendicular to the first direction, and Wherein an upper surface of the first molding structure is coplanar with an upper surface of the dummy chip.
18. 18. The semiconductor package according to claim 17, wherein a cross section of the channel in a second plane parallel to the first direction has a trapezoidal shape, and a width of the channel along the second direction is gradually reduced toward the uppermost first semiconductor chip, the second direction being perpendicular to the first direction.
19. 19. The semiconductor package of claim 17, wherein the channel comprises: a first portion having an X shape in a first plane, the first portion extending from a center of the dummy chip to four vertices of the dummy chip; a second portion having a plus sign shape in the first plane, the second portion extending from a center of the dummy chip to a center of four sides of the dummy chip, and The third portion has a rectangular ring shape in the first plane.
20. 20. The semiconductor package of any of claims 17-19, further comprising: an interposer between the first substrate and the base chip, and And a second semiconductor chip on the interposer, the second semiconductor chip being spaced apart from the base chip along a second direction perpendicular to the first direction.

Description

Semiconductor package The present application is based on and claims priority of korean patent application No. 10-2024-0155691 filed in the korean intellectual property office on 5 th month 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field The present disclosure relates to semiconductor packages. Background Recently, demand for portable devices has been rapidly increased in the market of electronic products, and thus miniaturization and weight saving of electronic components mounted in electronic products have been continuously demanded. For miniaturization and weight reduction of electronic components, semiconductor packages mounted in the electronic components have been required to process high-capacity data with small volumes and reduced defects. In addition, the semiconductor package may have a plurality of semiconductor chips stacked in a vertical direction to reduce the size of the semiconductor package. However, when a plurality of semiconductor chips are hybrid-bonded, the structural reliability of the semiconductor package may be degraded. Disclosure of Invention The present disclosure provides a semiconductor package with improved reliability. In addition, the problems to be solved by the technical concept of the present disclosure are not limited to the above-mentioned problems, and other problems may be clearly understood by those of ordinary skill in the art from the following description. In order to solve the technical problems of the present disclosure, the following semiconductor package is provided. According to an aspect of the present disclosure, a semiconductor package includes a base chip, a plurality of first semiconductor chips stacked on the base chip, a dummy chip stacked on an uppermost first semiconductor chip among the plurality of first semiconductor chips, and a molding member surrounding the base chip, the plurality of first semiconductor chips, and the dummy chip, wherein the dummy chip includes a channel extending from an upper surface of the dummy chip to a lower surface of the dummy chip, the channel having a shape extending from a center of the dummy chip to at least any one point located at an edge of the dummy chip in a horizontal direction in a top view, and the molding member fills the channel. According to another aspect of the present disclosure, a semiconductor package includes a base chip, a plurality of first semiconductor chips stacked on the base chip, and a dummy chip stacked on an uppermost first semiconductor chip among the plurality of first semiconductor chips and having a channel extending upward from a lower surface of the dummy chip, wherein the channel extends from a center of the dummy chip to at least four points located at an edge of the dummy chip in a top view, the plurality of first semiconductor chips are stacked by direct bonding, and the dummy chip is not electrically connected to the plurality of first semiconductor chips. According to another aspect of the present disclosure, a semiconductor package includes a first substrate, a base chip disposed on the first substrate, a plurality of first semiconductor chips stacked on the base chip, a dummy chip stacked on an uppermost first semiconductor chip among the plurality of first semiconductor chips and having a channel extending from a lower surface of the dummy chip to an upper surface of the dummy chip, a first molding member surrounding the base chip, the plurality of first semiconductor chips and the dummy chip and filling the channel, and a second molding member surrounding respective side surfaces of the first molding member and the base chip on the first substrate, wherein a dielectric layer of a semiconductor chip pad and a side surface surrounding the semiconductor chip pad is disposed on each of a lower surface and an upper surface of the plurality of first semiconductor chips, the channel has a shape extending from a center of the dummy chip to at least any four points located at an edge of the dummy chip in a horizontal direction in a top view, and the upper surface of the first molding member is coplanar with the upper surface of the dummy chip. Drawings Embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. Fig. 1 is a top view schematically showing a semiconductor package according to an embodiment. Fig. 2 is a cross-sectional view taken along line X1-X1' of the semiconductor package of fig. 1. Fig. 3 is a top view schematically showing a semiconductor package according to an embodiment. Fig. 4 is a cross-sectional view taken along line X1-X1' of the semiconductor package of fig. 3. Fig. 5 is a top view schematically showing a semiconductor package according to an embodiment. Fig. 6 is a cross-sectional view taken along line X1-X1' of the semiconductor package of fig. 5. Fig. 7 is a top view schematically showing a semicondu