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CN-122002824-A - Gallium oxide heterojunction diode with vertical structure and preparation method thereof

CN122002824ACN 122002824 ACN122002824 ACN 122002824ACN-122002824-A

Abstract

The invention discloses a gallium oxide heterojunction diode with a vertical structure and a preparation method thereof, comprising a gallium oxide epitaxial wafer, P-type oxides, arc-shaped structures, siO 2 field plates, anode electrodes, cathode electrodes and a cathode electrode, wherein the P-type oxides are positioned in the middle area of the upper surface of the gallium oxide epitaxial wafer, the two sides of the P-type oxides are in an arc-shaped structure, the curvature radius of the arc-shaped structures is smaller than 3 mu m, the SiO 2 field plates are positioned on the two sides of the P-type oxides and are in contact with the P-type oxides, and the anode electrodes are positioned on the P-type oxides and part of the SiO 2 field plates. The device structure designed by the invention effectively inhibits reverse leakage current, effectively improves the breakdown voltage of the device, and greatly improves the performance and reliability of the device.

Inventors

  • ZHOU HONG
  • YANG YUWEI
  • WANG CHENLU
  • SUN SIHAN
  • ZHANG JINCHENG
  • HAO YUE

Assignees

  • 西安电子科技大学

Dates

Publication Date
20260508
Application Date
20260129

Claims (10)

  1. 1. A gallium oxide heterojunction diode of vertical structure, characterized in that the gallium oxide heterojunction diode comprises: Gallium oxide epitaxial wafer; The two sides of the P-type oxide are in an arc structure, and the curvature radius of the arc structure is smaller than or equal to 3 mu m; SiO 2 field plates which are positioned at two sides of the P-type oxide and are in contact with the P-type oxide; The anode electrode is positioned on the P-type oxide and part of the SiO 2 field plate; and the cathode electrode is positioned on the lower surface of the gallium oxide epitaxial wafer.
  2. 2. The gallium oxide heterojunction diode of vertical structure of claim 1, wherein the radius of curvature of the arc-shaped structure is 1 μm to 3 μm.
  3. 3. The gallium oxide heterojunction diode of vertical structure of claim 1, wherein the P-type oxide comprises at least one of NiO, cu 2 O、Fe 3 O 4 .
  4. 4. The gallium oxide heterojunction diode of claim 1, wherein the P-type oxide has a thickness of 100nm to 200nm.
  5. 5. The gallium oxide heterojunction diode of claim 1, wherein the thickness of the SiO 2 field plates is 100 nm-200 nm.
  6. 6. The gallium oxide heterojunction diode of vertical structure of claim 1, wherein the anode electrode is of square or round configuration.
  7. 7. The preparation method of the gallium oxide heterojunction diode with the vertical structure is characterized by comprising the following steps of: obtaining a gallium oxide epitaxial wafer, and preprocessing the gallium oxide epitaxial wafer; Preparing a cathode electrode on the lower surface of the pretreated gallium oxide epitaxial wafer; depositing SiO 2 material in the middle area of the upper surface of the pretreated gallium oxide epitaxial wafer; Forming a groove mask by using photoresist, etching SiO 2 material in the middle area based on the groove mask to form a groove with an arc-shaped structure, and forming a SiO 2 field plate by using the residual SiO 2 material, wherein the curvature radius of the arc-shaped structure is smaller than or equal to 3 mu m; depositing a P-type oxide in the groove of the arc structure by using the residual photoresist as a hard mask; an anode electrode was prepared on a P-type oxide, partial SiO 2 field plate.
  8. 8. The method for fabricating a vertical-structured gallium oxide heterojunction diode as claimed in claim 7, wherein depositing SiO 2 material in the middle region of the upper surface of the pretreated gallium oxide epitaxial wafer comprises: And adopting a PECVD process or an ALD process, and depositing SiO 2 material with the thickness of 100-200 nm in the middle area of the upper surface of the pretreated gallium oxide epitaxial wafer at the temperature of 250-350 ℃.
  9. 9. The method of fabricating a gallium oxide heterojunction diode with a vertical structure as claimed in claim 7, wherein forming a trench mask by using photoresist, etching off the SiO 2 material in the middle region based on the trench mask to form a trench with an arc structure, comprises: Photoresist is coated on the whole SiO 2 material in a spin mode, a groove mask is formed by photoetching through an ultraviolet photoetching machine with the wavelength of 365nm, a groove of an arc-shaped structure is formed by etching the SiO 2 material in the middle area through an ICP etching machine based on the groove mask, and the curvature radius of the arc-shaped structure is 1-3 mu m.
  10. 10. The method of fabricating a vertical structure gallium oxide heterojunction diode as claimed in claim 7, wherein depositing a P-type oxide in the trench of the arc structure using the remaining photoresist as a hard mask comprises: And filling the P-type oxide with the thickness identical to that of the SiO 2 field plate in the groove with the arc structure by using the residual photoresist as a hard mask and adopting a radio frequency magnetron sputtering process or a pulse laser deposition process.

Description

Gallium oxide heterojunction diode with vertical structure and preparation method thereof Technical Field The invention belongs to the technical field of semiconductors, and particularly relates to a gallium oxide heterojunction diode with a vertical structure and a preparation method thereof. Background Gallium oxide (Ga 2O 3) materials are of great interest in power device applications. For example, beta-gallium oxide (beta-Ga 2O 3) is a material system with ultra-wide band gap (4.5 eV-4.9 eV) and high theoretical electric field strength (8 MV/cm). beta-Ga 2O3 realizes low-cost and high-quality homoepitaxial growth through a melt-grown single crystal substrate, so that the beta-Ga 2O3 becomes a main candidate material of a next-generation power device facing high-voltage and high-temperature application. With the continuous improvement of the large-area beta-Ga 2O3 wafer growth technology, the commercial feasibility of the technology is greatly improved. The attractive properties of beta-Ga 2O3, such as an ultra wide band gap of about 4.8eV and a high breakdown field exceeding 8MV/cm, make beta-Ga 2O3 a potential alternative material for high voltage silicon devices. For such excellent materials, both Ga2O3 based unipolar and bipolar power devices should be very popular in high power applications in electronic circuits. However, a key bottleneck that prevents the vertical Ga2O3 device from reaching its material limit Baliga figure of merit (Baliga's Figure of Merit, BFOM) is poor electric field control at the edges. A more critical issue is that conventional edge termination structures, such as field limiting rings (FIELD LIMITING RING, FLR) and junction extension terminals (Junction Termination Extension, JTE), cannot be used because the basic barrier to P-type doping makes it impractical in Ga2O 3. The gallium oxide material has high effective cavity quality, is extremely easy to form donor energy levels such as oxygen vacancies, defects and the like, has N-type conductivity even if undoped, and has the preparation of high-quality P-type gallium oxide. The gallium oxide Schottky barrier diode (Schottky Barrier Diode, SBD) is difficult to construct a homogeneous pn junction, can be only made into a unipolar device or depends on a heterojunction structure, so that the flexibility of the structural design of the device is limited, and the application of the gallium oxide Schottky barrier diode in complex scenes such as a complementary circuit is hindered. One existing solution is to implement a bipolar Ga2O3 diode with native P-type oxide, forming a P-N heterojunction diode (HJD) involving N-type Ga2O 3. The forward I-V characteristic of p-nHJD is similar to that of a unipolar SBD, exhibiting linear current conduction rather than bipolar behavior. The device not only has advantages in terms of increasing current density, but also can reduce on-resistance, thereby realizing strong surge current tolerance. Meanwhile, many terminal structures are designed, including ion implantation edge terminals, field plates, fin-shaped trench structures, etc., to continuously increase the breakdown voltage of the high-current gallium oxide diode. In recent progress, small vertical Ga2O3 SBD (< 100 μm diameter) employing ion implantation and bevel edge termination has shown enhanced breakdown voltages exceeding 1.0 kV. In addition, the optimized Ga2O3 groove type Schottky diode is combined with an Al2O3 dielectric layer, so that the breakdown voltage is about 3.4kV. However, these new methods require specialized equipment and complex process treatments, and require additional steps, and small-sized devices cannot provide large forward currents. Thus, some high power applications require large-sized devices to produce high forward currents while maintaining high breakdown voltages. Until now, large-size Ga2O3 SBD (> 1×10)2cm3 ) Still limited research is done. Device performance is affected by the high defect concentration of the active region, resulting in higher leakage current. These defects can cause serious performance and reliability problems at higher applied voltages. Disclosure of Invention In order to solve the problems in the prior art, the invention provides a gallium oxide heterojunction diode with a vertical structure and a preparation method thereof. The technical problems to be solved by the invention are realized by the following technical scheme: in a first aspect, an embodiment of the present invention provides a gallium oxide heterojunction diode with a vertical structure, where the gallium oxide heterojunction diode includes: Gallium oxide epitaxial wafer; The two sides of the P-type oxide are in an arc structure, and the curvature radius of the arc structure is smaller than or equal to 3 mu m; SiO 2 field plates which are positioned at two sides of the P-type oxide and are in contact with the P-type oxide; The anode electrode is positioned on the P-type oxide and part of the SiO 2 field plate; and the c