CN-122002826-A - Germanium-silicon heterojunction transistor and manufacturing method thereof

CN122002826ACN 122002826 ACN122002826 ACN 122002826ACN-122002826-A

Abstract

The application provides a germanium-silicon heterojunction transistor and a manufacturing method thereof, wherein in the manufacturing method, three layers of first cap layer sub-layers are formed firstly, after the three layers of first cap layer sub-layers are formed, the cyclic execution of etching is continuously adopted to supplement a second cap layer, the first cap layer sub-layers and supplement the second cap layer are deposited for a plurality of times, and a plurality of layers of stacked first cap layer sub-layers are formed between the bottom surfaces of an initial second cap layer and a supplement second cap layer and the upper surface of a germanium-silicon layer, wherein the initial second cap layer, the supplement second cap layer and the plurality of layers of stacked first cap layer sub-layers form an integral cap layer, the integral shape of the integral cap layer can be effectively improved, the thickness uniformity and the surface flatness of the integral cap layer are improved, the problems that the growth of a subsequent emitter is influenced and the radio frequency performance and other electrical performances of a device are influenced due to uneven cap layer growth in the manufacturing process of the traditional germanium-silicon heterojunction transistor are solved, and the RF performance of the device is improved and stabilized.

Inventors

LU MINGHUI
WANG MINGJIE
DU BAOTIAN
Bao Saisai
HUI KESHI
ZHANG SHOULONG

Assignees

华虹半导体(无锡)有限公司
华虹半导体制造(无锡)有限公司

Dates

Publication Date: 20260508
Application Date: 20260107

Claims (10)

1. A method of fabricating a germanium-silicon heterojunction transistor, comprising: Providing a substrate, wherein a first dielectric layer, an outer base region and a second dielectric layer are sequentially formed on the substrate, a first opening is formed in the outer base region, a second opening communicated with the first opening is formed in the first dielectric layer, the first opening and the second opening form a convex opening, the bottom of the convex opening is exposed out of part of the surface of the substrate, and the second dielectric layer covers the upper surface of the outer base region and the side wall of the first opening; A second step of growing a germanium-silicon layer upwards on the surface of the substrate of the bottom wall of the convex opening through a selective epitaxial process; A third step of growing a first capping layer sub-layer on the surface of the germanium-silicon layer through a selective epitaxial process, and simultaneously growing an initial second capping layer downwards at the bottom of the outer base region opposite to the bottom wall of the convex opening; Etching to remove the initial second cap layer with a certain width near the center of the second opening; a fifth step of forming a second layer of first cap layer sub-layer by continuing to grow upwards on the surface of the first cap layer sub-layer through a selective epitaxial process, and simultaneously forming a supplementary second cap layer by growing downwards on the rest initial second cap layer side and the bottom of the outer base region; a sixth step of etching to remove the supplementary second cap layer; A seventh step of forming a first cap layer sub-layer by continuing to grow upwards on the surface of the first cap layer sub-layer through a selective epitaxial process, and simultaneously forming a complementary second cap layer by growing downwards on the rest initial second cap layer side and the bottom of the outer base region; And an eighth step of circularly performing the sixth to seventh steps two to eight times until a space between the bottom surfaces of the initial second cap layer and the supplemental second cap layer and the upper surface of the silicon-germanium layer is filled with the stacked first cap layer sub-layers, wherein the initial second cap layer, the supplemental second cap layer, and the stacked first cap layer sub-layers constitute an integral cap layer.
2. The method of manufacturing a germanium-silicon heterojunction transistor according to claim 1, wherein in the third step, the gases involved in the selective epitaxy process at least comprise DCS gas and HCl gas, wherein the flow rate of DCS gas is 100 sccm-200 sccm, the flow rate of HCl gas is 50 sccm-400 sccm, the process temperature is 600 ℃ to 700 ℃, and the pressure of the process chamber is 10 Torr-100 Torr.
3. The method of manufacturing a germanium-silicon heterojunction transistor according to claim 1, wherein in the fourth step, the etching gas used for etching the initial second cap layer with a certain width at least comprises HCl, and the flow rate of HCl is 50sccm to 400sccm.
4. The method of manufacturing a silicon germanium heterojunction transistor according to claim 1, wherein after the space between the bottom surfaces of the initial second cap layer and the supplemental second cap layer in the eighth step and the upper surface of the silicon germanium layer is filled with the stacked first cap layer sub-layer, the total stacked thickness of the first cap layer sub-layer is 100 angstroms to 200 angstroms.
5. The method of manufacturing a germanium-silicon heterojunction transistor according to claim 1, wherein in the fifth step, the gases involved in the selective epitaxy process at least comprise DCS gas and HCl gas, wherein the flow rate of DCS gas is 100 sccm-200 sccm, the flow rate of HCl gas is 50 sccm-400 sccm, the process temperature is 600 ℃ to 700 ℃, and the pressure of the process chamber is 10 Torr-100 Torr.
6. The method of claim 1, wherein in the sixth step, the etching gas used for etching to remove the supplemental second cap layer comprises HCl, wherein the flow rate of HCl is 50sccm to 400sccm.
7. The method of manufacturing a germanium-silicon heterojunction transistor according to claim 1, wherein in the seventh step, the gases involved in the selective epitaxy process at least comprise DCS gas and HCl gas, wherein the flow rate of DCS gas is 100 sccm-200 sccm, the flow rate of HCl gas is 50 sccm-400 sccm, the process temperature is 600 ℃ to 700 ℃, and the pressure of the process chamber is 10 Torr-100 Torr.
8. The method of claim 1, wherein the supplemental second cap layer has a lateral width that is 20% of the lateral width of the initial second cap layer formed in the third step.
9. The method of manufacturing a germanium-silicon heterojunction transistor according to claim 1, wherein the first dielectric layer is made of silicon dioxide, the second dielectric layer is made of silicon nitride, and the outer base region is made of polysilicon.
10. A germanium-silicon heterojunction transistor, comprising: The substrate is sequentially provided with a first dielectric layer, an outer base region and a second dielectric layer, wherein a first opening is formed in the outer base region, a second opening communicated with the first opening is formed in the first dielectric layer, the first opening and the second opening form a convex opening, the bottom of the convex opening exposes part of the surface of the substrate, and the second dielectric layer covers the upper surface of the outer base region and the side wall of the first opening; a germanium-silicon layer which is formed by growing upwards on the surface of the substrate of the bottom wall of the convex opening through a selective epitaxial process; A stacked plurality of first cap layer sub-layers, the stacked plurality of first cap layer sub-layers being located on the silicon germanium layer; an initial second cap layer located at the bottom of a portion of the outer base region opposite the bottom wall of the convex opening; And a supplemental second cap layer located at a bottom of the remaining outer base region opposite to the bottom wall of the convex opening and located at the side of the supplemental second cap layer, wherein a space between a bottom surface of the supplemental second cap layer and the supplemental second cap layer to an upper surface of the silicon-germanium layer is filled with the stacked first cap layer sub-layers, wherein the supplemental second cap layer, and the stacked first cap layer sub-layers constitute an integral cap layer.

Description

Germanium-silicon heterojunction transistor and manufacturing method thereof Technical Field The application relates to the technical field of semiconductor manufacturing, in particular to a germanium-silicon heterojunction transistor and a manufacturing method thereof. Background The base region of the current bipolar Complementary Metal Oxide Semiconductor (CMOS) device with a node of 55nm adopts germanium-silicon epitaxial growth, wherein the selective germanium-silicon epitaxial scheme has simple process flow and easy integration. However, the scheme has the problem that the capping layer on the germanium-silicon layer grows unevenly, and is mainly characterized in that the upper surface of the capping layer is in a downward concave bending shape. Specifically, because in the current HBT (silicon germanium heterojunction transistor) device manufacturing process, a polysilicon outer base region is generally first made, then a silicon germanium layer (base region) is made, then a cap layer is deposited between the silicon germanium layer and the polysilicon outer base region, specifically, in the conventional silicon germanium heterojunction transistor manufacturing process, in the process of depositing the cap layer, the upper surface of the silicon germanium layer epitaxially grows monocrystalline silicon from bottom to top, and meanwhile, the bottom surface of the polysilicon outer base region epitaxially grows polycrystalline silicon from top to bottom, and the monocrystalline silicon and the polycrystalline silicon jointly form the cap layer. But the growth rate of the polysilicon is higher than that of the monocrystalline silicon, the polysilicon is easy to transversely grow after being contacted with the monocrystalline silicon, and finally the phenomenon that the polysilicon overflows out of one side face of one end of the polycrystalline silicon outer base region occurs, so that two ends of the cap layer are tilted, and the whole body of the cap layer is bent. The curved shape of the upper surface of the cap layer, which is concave downward, generally affects both aspects, wherein, on one hand, the curved shape of the upper surface of the cap layer, which is concave downward, can cause the angle of a sidewall structure (the sidewall structure is also positioned at the outer base side of polysilicon) deposited on the sidewall structure to change, thereby affecting the growth of a subsequent emitter, and on the other hand, the curved shape of the upper surface of the cap layer, which is concave downward, can cause a larger difference in electron transit time, and the difference in resistance of cap layers with different thicknesses is also different, thereby finally affecting the radio frequency performance and other electrical properties of the device. Disclosure of Invention The application provides a germanium-silicon heterojunction transistor and a manufacturing method thereof, which can solve the problems that the growth of a subsequent emitter is influenced and the radio frequency performance and other electrical performances of a device are influenced due to uneven growth of a cap layer between a germanium-silicon layer and a polycrystalline silicon outer base region in the traditional germanium-silicon heterojunction transistor manufacturing process. In one aspect, an embodiment of the present application provides a method for manufacturing a germanium-silicon heterojunction transistor, including: Providing a substrate, wherein a first dielectric layer, an outer base region and a second dielectric layer are sequentially formed on the substrate, a first opening is formed in the outer base region, a second opening communicated with the first opening is formed in the first dielectric layer, the first opening and the second opening form a convex opening, the bottom of the convex opening is exposed out of part of the surface of the substrate, and the second dielectric layer covers the upper surface of the outer base region and the side wall of the first opening; A second step of growing a germanium-silicon layer upwards on the surface of the substrate of the bottom wall of the convex opening through a selective epitaxial process; A third step of growing a first capping layer sub-layer on the surface of the germanium-silicon layer through a selective epitaxial process, and simultaneously growing an initial second capping layer downwards at the bottom of the outer base region opposite to the bottom wall of the convex opening; Etching to remove the initial second cap layer with a certain width near the center of the second opening; a fifth step of forming a second layer of first cap layer sub-layer by continuing to grow upwards on the surface of the first cap layer sub-layer through a selective epitaxial process, and simultaneously forming a supplementary second cap layer by growing downwards on the rest initial second cap layer side and the bottom of the outer base region; a sixth step of etching