CN-122002828-A - Small-size CT (computed tomography) open-pore groove type IGBT device and manufacturing method thereof

CN122002828ACN 122002828 ACN122002828 ACN 122002828ACN-122002828-A

Abstract

The invention discloses a small-size CT open-pore groove type IGBT device and a manufacturing method thereof, relating to the technical field of semiconductor devices, wherein the manufacturing method comprises the following steps of manufacturing a drift region, a carrier storage region, a body doping region, a source region and a groove gate structure on a semiconductor substrate; and etching the area between the trench gate structures by using a second mask to expose the body doped region, carrying out selective epitaxial growth of Si on the surface of the exposed body doped region, carrying out in-situ doping in the epitaxial growth process to form a selective epitaxial growth region, and forming a contact hole metal column and a surface metal layer on the selective epitaxial growth region. The invention can effectively solve the problem of high-quality ohmic contact at the bottom of the small-size CT opening, and simultaneously can avoid introducing extra photoetching steps, reduce the complexity of the process and improve the reliability of the device.

Inventors

WAN YIMIN
WANG XIUZHONG
FANG HUABIN
MA QINGHAI
WANG XIAOJUN

Assignees

上海华虹挚芯电子科技有限公司

Dates

Publication Date: 20260508
Application Date: 20260212

Claims (10)

1. The manufacturing method of the small-size CT open-pore groove type IGBT device is characterized by comprising the following steps of: Manufacturing a drift region, a carrier storage region, a body doping region, a source region and a trench gate structure on a semiconductor substrate; Etching the region between the trench gate structures by using a second mask to expose the body doped region; Performing selective epitaxial growth of Si on the surface of the exposed body doped region, and performing in-situ doping in the epitaxial growth process to form a selective epitaxial growth region; and forming a contact hole metal column and a surface metal layer on the selective epitaxial growth region.
2. The method of manufacturing a small-sized CT-aperture trench IGBT device of claim 1, wherein the step of etching using the second mask comprises etching the source region with the second mask as a barrier, and stopping etching inside the body doped region to expose the body doped region.
3. The method for manufacturing the small-size CT open-pore trench IGBT device according to claim 2, wherein the second mask is made of a multi-layer composite material and comprises a SiO 2 layer, a BPSG layer and a Si 3 N 4 layer in sequence from bottom to top, wherein the thickness of the SiO 2 layer is 1000A-3000A, the thickness of the BPSG layer is 3000A-6000A, the thickness of the Si 3 N 4 layer is 5000A-12000A, and after etching is finished, the SiO 2 layer and the BPSG layer remain to form a gate source isolation layer.
4. The method of claim 1, wherein the Si is doped in situ by selective epitaxial growth, the doping polarity is the same as that of the bulk doping region, and the doping concentration is 10 13 cm -3 -10 21 cm -3 opposite to the source region.
5. The method of fabricating a small-sized CT-opening trench IGBT device of claim 4 wherein said Si is selectively epitaxially grown using a silicon source gas and a dopant gas, the selective growth being performed only on the semiconductor surface of said body doped region and not on the opposite polarity source region sidewall.
6. The method of manufacturing a small-sized CT-open-pore trench IGBT device of claim 1, wherein in the step of manufacturing a drift region, a carrier storage region, a body doped region, and a source region, the carrier storage region and the body doped region are formed by maskless ion implantation and commonly activated by high-temperature annealing, and the source region is formed by maskless ion implantation and activated by high-temperature annealing.
7. The method of manufacturing a small-sized CT-open-pore trench IGBT device of claim 6, wherein in the step of manufacturing the trench gate structure, a trench is etched using a first mask, and the trench is oxidized and polysilicon filled to form a gate oxide layer and a polysilicon gate.
8. The method of manufacturing a small-sized CT-aperture trench IGBT device of claim 1, further comprising the step of sequentially forming a field stop region, a back doped region and a metal collector on the back of the semiconductor substrate.
9. A small-scale CT open-cell trench IGBT device made by the method of any of claims 1 to 8, the device comprising: A drift region; A carrier storage region located above the drift region; a body doped region located over the carrier storage region; a source region located over the body doped region; And a selective epitaxial growth region formed by selective epitaxial growth and in-situ doping of Si, the selective epitaxial growth region being located in the mesa region between the trench gates and in contact with the body doped region.
10. The small-sized CT aperture trench IGBT device of claim 9 comprising, in order in a vertical direction, a metal collector, a back side doped region, a field stop region, the drift region, the carrier storage region, the body doped region, the selective epitaxial growth region, the source region, a gate-source isolation layer, contact hole metal pillars, and a surface metal layer.

Description

Small-size CT (computed tomography) open-pore groove type IGBT device and manufacturing method thereof Technical Field The invention relates to the technical field of semiconductor devices, in particular to a small-size CT (computed tomography) open-pore groove type IGBT (insulated Gate Bipolar transistor) device and a manufacturing method thereof. Background In the development of power electronics technology, compared with a planar gate structure, a trench Insulated Gate Bipolar Transistor (IGBT) has been gradually mainstream because a conductive channel is formed vertically on a trench sidewall, eliminating a JFET region in a conventional sense, so that more effective channel width can be provided under the same chip area, on-resistance is significantly reduced, and current density and power density are improved. As technology nodes advance, cell size (pitch) continues to shrink, resulting in a dramatic decrease in the size of metal contact holes (CT holes) at the top of the cells. When the CT hole size is very small and the depth is kept unchanged, the depth-to-width ratio is increased, and a thin and deep hole is formed. When p+ ion implantation is performed in the P-body region (P-body) at the bottom of the CT hole to form an ohmic contact, the hole wall with high aspect ratio can severely block incident ions, resulting in ion implantation shadow effect, and only a very small amount of ions can reach the bottom of the hole. This results in a severely insufficient dose of boron ions implanted into the P-body region at the bottom of the hole, failing to form a high quality, low resistance P + ohmic contact. To solve the above-mentioned problems, the inventors know a related art technique in which the p+ implantation process is advanced before the CT hole is etched. Specifically, after the front end structures of the trench gate, the P-body, the n+ source region and the like are completed, single photolithography is performed at a time, and a new mask is used to define a region under the future CT hole where the p+ contact needs to be formed. And then, carrying out high-dose boron ion implantation on the surface of the flat silicon wafer to form a P+ region, and then carrying out annealing activation. And finally, carrying out normal CT hole photoetching and etching. However, this prior art solution has the following drawbacks: The process is complex, the cost is high, a special P+ photoetching mask plate and matched photoetching, cleaning and detecting procedures are added, and the manufacturing cost and the process complexity are directly increased. The overlay accuracy is extremely high, and the subsequent CT hole etching must be precisely aligned in three dimensions with the previously fabricated, invisible P+ region. Any minor misalignment may result in poor contact of the metal electrode with the p+ region or short circuit with the adjacent n+ source region, placing extremely high demands on the overlay accuracy of the lithographic apparatus. High dose P+ ion implantation causes serious lattice damage on the silicon surface, and is difficult to completely repair even after annealing, so that the high dose P+ ion implantation may become a hidden trouble of long-term reliability of a device. Thermal budget side effects the high temperature anneal process after P + implant causes additional longitudinal and lateral diffusion of the formed N + source impurities. This may result in channel length variations that affect the stability of the threshold voltage of the device, while also imparting additional thermal stress to the gate oxide layer of the trench sidewalls, which may compromise its reliability. Therefore, a novel trench type IGBT device structure and a method for manufacturing the same are needed in the art, which can effectively solve the problem of high-quality ohmic contact at the bottom of a small-sized CT opening, and simultaneously avoid introducing additional photolithography steps, reduce process complexity, and improve device reliability. Disclosure of Invention The invention aims to provide a small-size CT open-pore groove type IGBT device and a manufacturing method thereof, which are used for solving the problems existing in the prior art, effectively solving the problem of high-quality ohmic contact at the bottom of a small-size CT open-pore, avoiding introducing extra photoetching steps, reducing the process complexity and improving the reliability of the device. In order to achieve the above object, the present invention provides the following solutions: The invention provides a manufacturing method of a small-size CT open-pore groove type IGBT device, which comprises the following steps: Manufacturing a drift region, a carrier storage region, a body doping region, a source region and a trench gate structure on a semiconductor substrate; Etching the region between the trench gate structures by using a second mask to expose the body doped region; Performing selective epitaxial growt