CN-122002829-A - Semiconductor chip with double-sided grooves and manufacturing method

CN122002829ACN 122002829 ACN122002829 ACN 122002829ACN-122002829-A

Abstract

The invention relates to a semiconductor chip with double-sided grooves and a manufacturing method thereof. Belongs to the technical field of power semiconductor devices. The single-groove chip mainly solves the problems of low production efficiency, high cost and limited forward and reverse blocking voltage improvement of the existing single-groove chip. The low-resistance conductive current channel is mainly characterized in that the grooves are terminal double-sided grooves and are symmetrically arranged at P-N junction terminals of an N-type substrate, an anode P layer and a cathode P layer respectively, a protective layer is arranged on the inner surface of each groove, cathode P short-circuit points and cathode P+ short-circuit points embedded in the cathode P short-circuit points are uniformly arranged in a cathode N+ region, and a low-resistance conductive current channel is formed. The invention cancels the design of the P-type through ring structure, adopts the low-concentration P-type doping and the high-concentration P+ design, can reduce the short-circuit through resistance, improves the through-current capability and the blocking voltage of the chip, and is mainly used for manufacturing the medium-voltage and high-voltage power semiconductor device chip.

Inventors

ZHANG QIAO
LIU XIAOLI
YAN JIASHENG
WANG WEI
LIU XIAO
MA LUYAO

Assignees

湖北台基半导体股份有限公司

Dates

Publication Date: 20260508
Application Date: 20260313
Priority Date: 20251113

Claims (10)

1. A semiconductor chip with double-sided grooves comprises an anode P+ layer (2), an anode P layer (3), an N-type substrate (4), a cathode P layer (5), a gate P+ (6), a cathode N+ (8) and grooves, wherein the cathode P layer (5) and the anode P layer (3) are symmetrically arranged on two sides of the N-type substrate (4), the gate P+ (6) and the cathode N+ (8) are arranged on the surface of the cathode P layer (5) far away from the N-type substrate (4), an anode metal layer (1) is arranged on the surface of the anode P+ layer (2) to form an electrode anode (A), a gate metal layer (7) is arranged on the surface of the gate P+ (6) to form an electrode gate (G), the cathode P layer (5) is provided with a cathode metal layer (11) through the surface of the cathode N+ (8) to form an electrode cathode (K), the gate metal layer (7) and the cathode metal layer (11) are provided with a gate cathode isolation region (15), and the double-sided groove is a terminal groove, and is respectively and symmetrically arranged on the junction between the anode P+ layer (4) and the cathode P layer (3) and the anode P layer (1) and the terminal P-P layer (j), the inner surface of the groove is provided with a protective layer, and cathode P short-circuit points (9) and cathode P+ short-circuit points (10) embedded in the cathode P short-circuit points (9) are uniformly arranged in the area of the cathode N+ (8) to form a low-resistance conductive current channel.
2. The semiconductor chip of claim 1, wherein the depth of the trench is 120-150 μm.
3. A semiconductor chip with double-sided grooves as claimed in claim 1 or 2, wherein the protective layer comprises a SIPOS layer (12), a glass passivation film (13) and a SiO 2 passivation layer (14) from inside to outside.
4. The semiconductor chip of claim 3, wherein the junction depth of the anode P layer (3) and the cathode P layer (5) is 75-100 μm.
5. The semiconductor chip with the double-sided groove according to any one of claims 1-2 and 4 is characterized in that the surface concentration of the anode P+ layer (2) is 0.6-8.0X10 20 /cm 3 , the junction depth is 5-15 μm, the surface concentrations of the anode P layer (3) and the cathode P layer (5) are 0.2-6.0X10 16 /cm 3 , the depth is 75-100 μm, the cathode N+ (8) is an N-type doped region, the surface concentration of the cathode N+ (8) is 0.9-8.8X10 20 /cm 3 , the depth is 15-25 μm, the cathode P-type short-circuit points (9) are cylindrical, are uniformly arranged in a regular square shape or a regular triangle shape, have a diameter of 0.10-0.36 mm and are connected with the cathode P layer (5) under the cathode N+ (8) doped region, the cathode P+ short-circuit points (10) are embedded in the cathode P-type short-circuit points (9), the diameter is 0.10-0.30 mm, and the surface concentration of the cathode P+ short-circuit points (10) is 15-25 μm, and the surface concentration of the cathode P+ short-circuit points (10) is 0.37-5 μm.
6. A semiconductor chip with double sided trench as claimed in claim 1-2 or 4, wherein the anode metal layer (1) is Ni-Ag, al-Ti-Ni-Ag or Al-Ti-Ni-Au.
7. A semiconductor chip with double sided trench as claimed in claim 1-2 or 4, wherein the cathode metal layer (11) is Al, al-Ti-Ni-Ag or Al-Ti-Ni-Au.
8. A semiconductor chip with double-sided grooves as claimed in any one of claims 1-2 and 4, wherein the surface of the SiO 2 passivation layer is provided with a protective layer (16), and the protective layer (16) is polyimide.
9. A method for manufacturing a semiconductor chip with double-sided grooves is characterized by comprising the following steps: (1) Selecting an N type <111> crystal orientation silicon wafer as a substrate, wherein the thickness of the silicon wafer is 400-500 mu m, the resistivity is 50-80 omega cm or 80-100 omega cm, and the diameter is 101.6-150 double-sided chemical corrosion polishing; (2) P diffusion, namely pre-depositing aluminum on both sides of a wafer at the temperature of 950-1150 ℃ after the wafer is cleaned, then performing low-concentration distribution diffusion and oxidization at the temperature of 1200-1250 ℃ for 10-30 hours to form a P1 region and a P2 region, wherein the junction depth is 70-80 mu m, and the surface impurity concentration is 0.35-8.5X10 16 /cm 3 ; (3) N+ photoetching, namely coating photoresist on the cathode of the wafer, exposing, developing, protecting the anodic oxidation layer, removing the oxidation layer of the cathode N+ window area, and double-sided etching the mark, and then removing the photoresist; (4) N+ diffusion, namely pre-depositing or injecting phosphorus at the temperature of 1000-1125 ℃ after cleaning the wafer, then pushing and oxidizing at the temperature of 1120-1250 ℃ for 8-12 hours to form a P1-N1-P2-N+ structure, wherein the impurity concentration on the surface of the cathode N+ (8) is 0.58-8.0X10 20 /cm 3 , and the junction depth is 12-20 mu m; (5) P+ photoetching, namely coating photoresist on the cathode of a wafer, exposing and developing, removing an oxide layer of a gate P+ and cathode P+ window area, removing an anode surface oxide layer, and then removing the photoresist; (6) P+ diffusion, namely spraying boron on the surface of a wafer, and diffusing to form an anode P+ layer (2), a gate P+ (6) and a cathode P+ short-circuit point (10), wherein the depth of the anode P+ layer (2) is 5-15 mu m, the depth of the gate P+ (6) and the cathode P+ short-circuit point (10) is 5-10 mu m, the surface impurity concentration of the anode P+ layer (2) is 0.6-8.0X10 20 /cm 3 , and the surface impurity concentration of the gate P+ (6) and the cathode P+ short-circuit point (10) is 4.5-9.0X10 19 /cm 3 ; the propulsion condition is 1180-1250 ℃, N 2 =6L/min,O 2 = 0.5L/min, and the time is 60-200 min; (7) Photoetching a groove region, namely coating photoresist on the cathode and anode of a wafer, exposing and developing to remove the photoresist in a groove window region; (8) Groove etching, namely double-sided annular groove etching, wherein the groove digging depth is 120-150 mu m, and the width of the groove digging surface is 400-600 mu m; (9) SIPOS deposition, namely after the wafer is cleaned, depositing a SIPOS film at 500-800 ℃ in the exposed P-N junction area of the groove to form a SIPOS layer (12) and protecting the table top; (10) Glass passivation, namely coating glass powder in a wafer groove by adopting a knife scraping or photoresistance method, and then sintering at a low temperature of 500-580 ℃ and a high temperature of 800-850 ℃ to form a glass passivation film (13); (11) Depositing a SiO 2 passivation layer (14) on the surface of the wafer at the temperature of 400-600 ℃ by LTO deposition; (12) BOE etching, namely coating photoresist on the surface of the wafer, exposing and developing to remove a SIPOS (silicon on insulator) and SiO 2 passivation layer in a window area, and then removing the photoresist; (13) The first metal deposition, namely, after the wafer is cleaned, evaporating a metal conducting layer on the two sides of the wafer, wherein the thickness of the metal layer on the anode surface is 2-4 mu m, and the thickness of the metal layer on the cathode surface is 6-12 mu m; (14) The first metal etching, namely respectively coating photoresist on the two surfaces of the wafer surface, exposing and developing to remove the metal layers of the window area at the position of the groove and the gate cathode isolation area, and then removing the photoresist; (15) Alloying the metal conductive layer with the wafer at 500-550 ℃ to increase ohmic contact and welding force between the metal and the wafer; (16) The second metal deposition, namely, after the wafer is cleaned, sequentially depositing a plurality of metal conducting layers Ti-Ni-Ag or Ti-Ni-Au on the anode surface of the wafer, wherein the thicknesses of the metal conducting layers Ti-Ni-Ag or Ti-Ni-Au are respectively 0.2 mu m, 0.5 mu m and 1.2 mu m; (17) Coating photoresist on the anode of the wafer, exposing, developing, removing the multi-layer metal conductive layer in the window area of the groove position, and then removing the photoresist; (18) And testing and sorting semiconductor chip parameters, and separating, dicing, inspecting and identifying the chips.
10. The method of manufacturing a semiconductor chip with double-sided trench as claimed in claim 9, wherein polyimide is coated on both sides of the wafer surface between the steps (17) and (18), and then the polyimide on the metal layer is removed by photolithography, and SiO is deposited on the wafer 2 A passivation layer (14) is formed on the surface of the passivation layer (16).

Description

Semiconductor chip with double-sided grooves and manufacturing method Technical Field The invention belongs to the technical field of power semiconductor device design and manufacture, and particularly relates to a semiconductor chip with double-sided grooves and a manufacturing method thereof. Background In the manufacturing of chips for power semiconductor devices, mesa etching technology is still widely used in the manufacturing of chips for module power semiconductor devices, particularly in square power semiconductor chips, as shown in fig. 1, a semiconductor chip structure with a single-groove passivation layer mesa technology is adopted for a forward blocking voltage terminal, a P-type through ring is adopted for a terminal during reverse blocking voltage, long-time push-in diffusion is required for forming the P-type through ring, the thicker the silicon wafer is, the longer the silicon wafer is, the thicker the silicon wafer is, the punch-through diffusion is required to be completed, so that the production efficiency is reduced and the cost is high, and meanwhile, the forward blocking voltage and the reverse blocking voltage are promoted by a PN junction terminal technology. Disclosure of Invention The invention aims to provide a semiconductor chip with double-sided grooves and a method for implementing the semiconductor chip with double-sided grooves, so as to solve the problems of low production efficiency, higher cost and difficult improvement of forward and reverse blocking voltage. The technical scheme of the chip is that the semiconductor chip comprises an anode P+ layer, an anode P layer, an N-type substrate, a cathode P layer, a gate P+, a cathode N+ and grooves, wherein the cathode P layer and the anode P layer are symmetrically arranged on two sides of the N-type substrate, the gate P+ and the cathode N+ are arranged on the surface of the cathode P layer far away from the N-type substrate, an anode metal layer is arranged on the surface of the anode P+ layer to form an electrode anode, the gate metal layer is arranged on the surface of the gate P+ to form an electrode gate, the cathode P layer is provided with a cathode metal layer on the surface of the cathode N+ to form an electrode cathode, and a gate cathode isolation region is arranged between the gate metal layer and the cathode metal layer. In the technical scheme of the chip, the depth of the groove is 120-150 mu m. In the technical scheme of the chip, the protective layer comprises a SIPOS layer, a glass passivation film and a SiO 2 passivation layer from inside to outside. In the technical scheme of the chip, the junction depth of the anode P layer and the cathode P layer is 75-100 mu m. According to the technical scheme of the chip, the surface concentration of the anode P+ layer is 0.6-8.0X10 20/cm3, the junction depth is 5-15 mu m, the surface concentrations of the anode P layer and the cathode P layer are 0.2-6.0X10 16/cm3, the depth is 75-100 mu m, the cathode N+ is an N-type doped region, the surface concentration of the cathode N+ is 0.9-8.8X10 20/cm3, the depth is 15-25 mu m, the cathode P-type short-circuit points are cylindrical, are uniformly arranged in a regular quadrangle or regular triangle, have the diameter of 0.10-0.36 mm, are connected with the cathode P layer under the cathode N+ doped region, the cathode P+ short-circuit points are embedded in the cathode P-type short-circuit points, the diameter of 0.10-0.30 mm, the surface concentrations of the cathode P+ short-circuit points and the gate P+ are 4.5-9.0X10. 10 19/cm3, and the junction depth of the cathode P+ is 5-10 mu m. In the technical scheme of the chip, the anode metal layer is Ni-Ag, al-Ti-Ni-Ag or Al-Ti-Ni-Au. In the technical scheme of the chip, the cathode metal layer is Al, al-Ti-Ni-Ag or Al-Ti-Ni-Au. In the technical scheme of the chip, a protective layer is arranged on the surface of the SiO 2 passivation layer, and the protective layer is polyimide. The technical proposal of the manufacturing method of the invention is that the manufacturing method of the semiconductor chip with double-sided grooves is characterized by comprising the following steps: (1) Selecting an N type <111> crystal orientation silicon wafer as a substrate, wherein the thickness of the silicon wafer is 400-500 mu m, the resistivity is 50-80 omega cm or 80-100 omega cm, and the diameter is 101.6-150 double-sided chemical corrosion polishing; (2) P diffusion, namely pre-depositing aluminum on both sides of a wafer at the temperature of 950-1150 ℃ after the wafer is cleaned, then performing low-concentration distribution diffusion and oxidization at the temperature of 1200-1250 ℃ for 10-30 hours to form a P1 region and a P2 region, wherein the junction depth is 70-80 mu m, and the surface impurity concentration is 0.35-8.5X10 16/cm3; (3) N+ photoetching, namely coating photoresist on the cathode of the wafer, exposing, developing, protecting the anodic oxidation layer, remo