CN-122002830-A - Semiconductor device and method of forming the same

Abstract

The invention relates to a semiconductor device and a method for forming the same. In the forming method, an MOS device is formed in an active region, at least one groove is formed in a source drain lead-out region, when a self-aligned metal silicidation process is performed, metal silicidation reaction is performed on the inner surface of the groove and the surface of a source drain region outside the groove to form a metal silicide layer, so that the upper surface of the metal silicide layer positioned in the source drain lead-out region is a curved surface, the metal silicide layer with the curved surface is exposed by a source drain through hole formed corresponding to the source drain lead-out region, and compared with the situation that the groove is not formed in the source drain lead-out region before the self-aligned metal silicidation process, the area of the metal silicide layer exposed by the source drain through hole is increased, and after a source drain plug is formed, the contact area between the source drain plug and the metal silicide layer exposed by the source drain through hole is larger, so that the contact resistance between the contact plug and the corresponding source drain region can be reduced, and the device performance is improved.

Inventors

• Request for anonymity
• Request for anonymity

Assignees

• 青岛澳柯玛云联信息技术有限公司

Dates

Publication Date

20260508

Application Date

20241105

Claims (10)

1. 1. A method of forming a semiconductor device, comprising: Providing a substrate, wherein the substrate comprises a trench isolation and an active area defined by the trench isolation, the active area is provided with a source drain forming area for forming a source drain area of a MOS device, and the surface of the source drain forming area comprises a source drain leading-out area for connecting a source drain plug; Forming a Metal Oxide Semiconductor (MOS) device in the active region, and forming at least one groove in the source drain lead-out region, wherein the MOS device comprises a grid electrode formed on the active region and source drain regions respectively formed in the active region at two sides of the grid electrode, and the depth of the source drain regions is larger than that of the groove; performing a self-aligned metal silicidation process to enable the inner surface of the groove and the surface of the source drain region outside the groove to generate metal silicidation reaction to form a metal silicide layer, wherein the upper surface of the metal silicide layer positioned in the source drain lead-out region is a curved surface; covering a dielectric layer on the substrate, forming a source-drain through hole penetrating the dielectric layer and exposing the metal silicide layer corresponding to the source-drain lead-out region, and And filling conductive materials in the source-drain through holes to form source-drain plugs, wherein the source-drain plugs are contacted with the metal silicide layers exposed by the source-drain through holes so as to be connected with the corresponding source-drain regions.
2. 2. The method of forming of claim 1, wherein after forming the recess, a surface of the source drain lead-out region includes an inner surface of the recess and a portion of the active region surface outside the recess.
3. 3. The method of forming of claim 1, wherein the source drain lead-out region forms at least two recesses.
4. 4. The method of forming of claim 1, wherein the recess is formed by etching the substrate before or after forming the MOS device or during forming the MOS device.
5. 5. The forming method according to any one of claims 1 to 4, wherein forming the MOS device and the recess includes: Forming a gate dielectric material layer on the surface of the substrate; Etching the gate dielectric material layer to enable the gate dielectric material layer to be provided with an opening positioned on the forming area of the groove; Forming a gate material layer on the substrate; Etching the gate material layer and the gate dielectric material layer to form a gate and a gate dielectric layer between the gate and the active region while forming the recess in the substrate corresponding to the opening in the gate dielectric material layer, and Forming side walls positioned on the gate dielectric layer and the side surfaces of the gate and source and drain regions respectively positioned on two sides of the gate, wherein the surfaces of the source and drain regions comprise source and drain lead-out regions, and the source and drain lead-out regions form at least one groove.
6. 6. The method of forming of claim 5, wherein in the process of etching the gate dielectric material layer to form the opening, the substrate exposed by the opening is also etched.
7. 7. A semiconductor device, comprising: a substrate comprising trench isolation and an active region defined by the trench isolation; The MOS device comprises a grid electrode formed on the active region and source and drain regions respectively formed on the two sides of the grid electrode and the active region, wherein the surface of the source and drain regions comprises a source and drain extraction region which comprises at least one groove and a part of the source and drain regions positioned outside the groove, and the depth of the source and drain regions is larger than that of the groove; the metal silicide layer is formed on the surfaces of the source and drain regions in the groove and outside the groove, and the upper surface of the metal silicide layer positioned in the source and drain lead-out region is a curved surface; A dielectric layer covering the substrate, the dielectric layer having source and drain vias formed therein corresponding to the source and drain lead-out regions, the source and drain vias exposing the metal silicide layer corresponding to the source and drain lead-out regions, and And a source-drain plug filling the source-drain via hole and contacting the metal silicide layer exposed by the corresponding source-drain via hole so as to be connected with the corresponding source-drain region.
8. 8. The semiconductor device of claim 7, wherein the source drain lead-out region comprises at least two recesses and a region between the at least two recesses.
9. 9. The semiconductor device of claim 7, wherein a cross-section of the recess comprises at least one of a circle, a semicircle, an ellipse, a semi-ellipse, and a polygon.
10. 10. The semiconductor device according to any one of claims 7 to 9, wherein the metal silicide layer includes at least one of nickel silicide, titanium silicide, tantalum silicide, tungsten silicide, and cobalt silicide.

Description

Semiconductor device and method of forming the same Technical Field The present disclosure relates to integrated circuit fabrication, and more particularly, to a semiconductor device and a method of forming the same. Background The self-aligned metal silicide (Salicide) process is widely applied to semiconductor process devices, and enables metal and semiconductor silicon (such as monocrystalline silicon or polycrystalline silicon) to form ohmic contact through the metal silicide, so that the contact resistance and series resistance of the metal and the silicon can be reduced, and the transmission speed of the device is improved. As shown in fig. 1, in a conventional semiconductor process, after forming a gate electrode G and side walls (not shown) and source and drain regions (including a source region S and a drain region D) on a surface region of a substrate 11, a metal silicide layer 12 is formed on the surface of the source and drain regions and the surface of the gate electrode G by using a self-aligned metal silicide process, a dielectric layer 13 is then covered on the substrate 11, a via hole 13a exposing the metal silicide layer 12 is formed corresponding to the source and drain regions, a via hole 13b exposing the metal silicide layer 12 is formed in the dielectric layer 13 corresponding to the gate electrode G, and conductive materials are filled in the via hole 13a and the via hole 13b, thereby forming a source and drain plug (not shown) contacting the corresponding source and drain regions through the metal silicide layer 12 and a gate plug contacting the gate electrode G through the metal silicide layer 12. With the development of technology nodes, the line width of the device is continuously reduced, and the cross section of the through hole 13a in the prior art is smaller and smaller, so that the contact resistance between the source drain plug and the corresponding source drain region is increased, further, the RC (resistance capacitance) of the device is increased, and the performance of the device such as the response speed is affected. Although the self-aligned metal silicide process by selecting the metal material with lower resistivity plays a role in reducing the contact resistance, as the line width of the device is reduced, the contact resistance between the source-drain plug and the corresponding source-drain region is still larger, and the performance of the device is affected. Disclosure of Invention In order to reduce contact resistance between a source-drain plug and a corresponding source-drain region, the invention provides a semiconductor device and a method for forming the semiconductor device. In one aspect, the present invention provides a method of forming a semiconductor device, the method comprising: Providing a substrate, wherein the substrate comprises a trench isolation and an active area defined by the trench isolation, the active area is provided with a source drain forming area for forming a source drain area of a MOS device, and the surface of the source drain forming area comprises a source drain leading-out area for connecting a source drain plug; Forming a Metal Oxide Semiconductor (MOS) device in the active region, and forming at least one groove in the source drain lead-out region, wherein the MOS device comprises a grid electrode formed on the active region and source drain regions respectively formed in the active region at two sides of the grid electrode, and the depth of the source drain regions is larger than that of the groove; performing a self-aligned metal silicidation process to enable the inner surface of the groove and the surface of the source drain region outside the groove to generate metal silicidation reaction to form a metal silicide layer, wherein the upper surface of the metal silicide layer positioned in the source drain lead-out region is a curved surface; covering a dielectric layer on the substrate, forming a source-drain through hole penetrating the dielectric layer and exposing the metal silicide layer corresponding to the source-drain lead-out region, and And filling conductive materials in the source-drain through holes to form source-drain plugs, wherein the source-drain plugs are contacted with the metal silicide layers exposed by the source-drain through holes so as to be connected with the corresponding source-drain regions. Optionally, after the recess is formed, the surface of the source drain lead-out region includes an inner surface of the recess and a portion of the active region surface outside the recess. Optionally, the source drain lead-out area forms at least two grooves. . Optionally, the recess is formed by etching the substrate before or after forming the MOS device or during forming the MOS device. Optionally, forming the MOS device and the recess includes: Forming a gate dielectric material layer on the surface of the substrate; Etching the gate dielectric material layer to enable the gate dielectric material