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CN-122002833-A - Transistor and preparation method thereof

CN122002833ACN 122002833 ACN122002833 ACN 122002833ACN-122002833-A

Abstract

The present disclosure provides a transistor and a method of manufacturing the same. The preparation method comprises the steps of manufacturing a channel layer, manufacturing a barrier layer on the channel layer, manufacturing a first dielectric layer on the barrier layer, manufacturing a first metal layer on the first dielectric layer, manufacturing a second dielectric layer on the first metal layer by adopting a plasma energy gradient increasing PECVD process, and manufacturing a second metal layer on the second dielectric layer.

Inventors

  • FANG YAN
  • SUN JIAN
  • GU HAO

Assignees

  • 京东方华灿光电(浙江)有限公司

Dates

Publication Date
20260508
Application Date
20251217

Claims (10)

  1. 1. A transistor manufacturing method, characterized in that the transistor manufacturing method comprises: Manufacturing a channel layer (101); -fabricating a barrier layer (102) on the channel layer (101); Manufacturing a first dielectric layer (103) on the barrier layer (102); manufacturing a first metal layer (104) on the first dielectric layer (102); a second dielectric layer (105) is manufactured on the first metal layer (104) by adopting a plasma energy gradient increasing PECVD process; a second metal layer (106) is formed on the second dielectric layer (105).
  2. 2. The method of manufacturing a transistor according to claim 1, wherein said fabricating a second dielectric layer (105) on said first metal layer (104) using a plasma-energy gradient-enhanced PECVD process, comprises: A PECVD device is used for manufacturing the Si compound layer, and the radio frequency power gradient of the PECVD device is increased in the process of manufacturing the second dielectric layer (105).
  3. 3. The method according to claim 2, characterized in that the rf power of the PECVD apparatus is increased in a gradient of 100-300 w during the fabrication of the second dielectric layer (105), the gradient of the rf power increase of the PECVD apparatus being 95-105 w.
  4. 4. The method of manufacturing a transistor according to claim 2, wherein the Si compound layer manufactured by using the PECVD apparatus comprises: And growing a SiO 2 layer under the conditions that the pressure is 2000-5000 mM, the SiH 4 flow rate is 80-260 sccm, the N 2 O flow rate is 1200-5000 sccm, the distance between an air outlet of the PECVD equipment and a wafer is 12.5-13.2 mm, and the growth time is 29-210 s.
  5. 5. The method of manufacturing a transistor according to any one of claims 1 to 4, wherein the thickness of the second dielectric layer (105) is 700 to 4000nm.
  6. 6. A method of manufacturing a transistor according to any of claims 1 to 4, characterized in that the first dielectric layer is made on the barrier layer (102) comprising: Forming a SiN layer on the barrier layer (102) by using MOCVD equipment, wherein the SiN layer is used as a first dielectric sub-layer (1031); an AlN layer is manufactured on the first dielectric sub-layer (1031) by using MOCVD equipment and is used as a second dielectric sub-layer (1032); Forming a SiN layer on the second dielectric sub-layer (1032) using MOCVD equipment as a third dielectric sub-layer (1033); using an LPCVD apparatus to produce a SiN layer on the third dielectric sub-layer (1033) as a fourth dielectric sub-layer (1034); -fabricating a SiN layer on the fourth dielectric sub-layer (1034) using a PECVD apparatus as a fifth dielectric sub-layer (1035); manufacturing a SiN layer on the fifth dielectric sub-layer (1035) by using PECVD equipment to serve as a sixth dielectric sub-layer (1036); And manufacturing a SiO 2 layer on the sixth dielectric sub-layer (1036) by using a PECVD device, wherein the first dielectric layer comprises the first dielectric sub-layer (1031) to the seventh dielectric sub-layer (1037) as a seventh dielectric sub-layer (1037).
  7. 7. The method according to claim 6, wherein the thickness of the first dielectric sub-layer (1031) is 50-60 nm, the thickness of the second dielectric sub-layer (1032) is 1-5 nm, the thickness of the third dielectric sub-layer (1033) is 3-8 nm, the thickness of the fourth dielectric sub-layer (1034) is 290-310 nm, the thickness of the fifth dielectric sub-layer (1035) is 590-610, the thickness of the sixth dielectric sub-layer (1036) is 490-510 nm, and the thickness of the seventh dielectric sub-layer (1037) is 690-710 nm.
  8. 8. The transistor is characterized by comprising a channel layer (101), a barrier layer (102), a first dielectric layer (103), a first metal layer (104), a second dielectric layer (105) and a second metal layer (106); The channel layer (101), the barrier layer (102), the first dielectric layer (103), the first metal layer (104), the second dielectric layer (105) and the second metal layer (106) are sequentially stacked; the second dielectric layer (105) is a Si compound layer manufactured by adopting a plasma energy gradient increasing PECVD process.
  9. 9. The transistor of claim 8, wherein the thickness of the second dielectric layer (105) is 700-4000 nm.
  10. 10. The transistor according to claim 8 or 9, wherein the first dielectric layer (103) comprises a first dielectric sub-layer (1031), a second dielectric sub-layer (1032), a third dielectric sub-layer (1033), a fourth dielectric sub-layer (1034), a fifth dielectric sub-layer (1035), a sixth dielectric sub-layer (1036) and a seventh dielectric sub-layer (1037) stacked in this order; The thickness of the first dielectric sub-layer (1031) is 50-60 nm, the thickness of the second dielectric sub-layer (1032) is 1-5 nm, the thickness of the third dielectric sub-layer (1033) is 3-8 nm, the thickness of the fourth dielectric sub-layer (1034) is 290-310 nm, the thickness of the fifth dielectric sub-layer (1035) is 590-610, the thickness of the sixth dielectric sub-layer (1036) is 490-510 nm, and the thickness of the seventh dielectric sub-layer (1037) is 690-710 nm.

Description

Transistor and preparation method thereof Technical Field The disclosure relates to the field of power devices, and in particular relates to a transistor and a preparation method thereof. Background The high electron mobility transistor (High Electron Mobility Transistor, HEMT) is a heterojunction field effect transistor and is widely applied to the fields of wireless communication, automobile electronics and the like. The related art provides a transistor, which comprises a channel layer, a barrier layer, a first dielectric layer, a first metal layer, a second dielectric layer and a second metal layer, wherein the barrier layer, the first dielectric layer, the first metal layer, the first dielectric layer and the second metal layer are sequentially laminated on the channel layer. In the process of manufacturing the second dielectric layer, the second dielectric layer is easy to crack due to larger stress, so that the yield of the transistor is reduced. Disclosure of Invention The embodiment of the disclosure provides a transistor and a preparation method thereof, which can obviously reduce the stress of a dielectric layer and avoid the occurrence of cracks of the dielectric layer. The technical scheme is as follows: in one aspect, a transistor fabrication method is provided, the transistor fabrication method comprising: manufacturing a channel layer; Manufacturing a barrier layer on the channel layer; manufacturing a first dielectric layer on the barrier layer; Manufacturing a first metal layer on the first dielectric layer; a second dielectric layer is manufactured on the first metal layer by adopting a plasma energy gradient increasing PECVD process; and manufacturing a second metal layer on the second dielectric layer. Optionally, the fabricating a second dielectric layer on the first metal layer by using a plasma energy gradient increasing PECVD process includes: and manufacturing the Si compound layer by adopting a PECVD device, wherein the radio frequency power gradient of the PECVD device is increased in the process of manufacturing the second dielectric layer. Optionally, in the process of manufacturing the second dielectric layer, the radio frequency power of the PECVD device is increased in a gradient manner within a range of 100-300W, and the gradient of the increase of the radio frequency power of the PECVD device is 95-105W. Optionally, the Si compound layer fabricated by using a PECVD apparatus includes: And growing a SiO 2 layer under the conditions that the pressure is 2000-5000 mM, the SiH 4 flow rate is 80-260 sccm, the N 2 O flow rate is 1200-5000 sccm, the distance between an air outlet of the PECVD equipment and a wafer is 12.5-13.2 mm, and the growth time is 29-210 s. Optionally, the thickness of the second dielectric layer is 700-4000 nm. Optionally, fabricating a first dielectric layer on the barrier layer, including: using MOCVD equipment to manufacture a SiN layer on the barrier layer as a first dielectric sub-layer; manufacturing an AlN layer on the first dielectric sub-layer by using MOCVD equipment to serve as a second dielectric sub-layer; using MOCVD equipment to manufacture a SiN layer on the second dielectric sub-layer as a third dielectric sub-layer; Manufacturing a SiN layer on the third dielectric sub-layer by using LPCVD equipment to serve as a fourth dielectric sub-layer; Manufacturing a SiN layer on the fourth dielectric sub-layer by using PECVD equipment, and taking the SiN layer as a fifth dielectric sub-layer; Manufacturing a SiN layer on the fifth dielectric sub-layer by using PECVD equipment, and taking the SiN layer as a sixth dielectric sub-layer; and manufacturing a SiO 2 layer on the sixth dielectric sub-layer by using PECVD equipment, wherein the first dielectric layer comprises the first dielectric sub-layer to the seventh dielectric sub-layer as a seventh dielectric sub-layer. Optionally, the thickness of the first dielectric proton layer is 50-60 nm, the thickness of the second dielectric proton layer is 1-5 nm, the thickness of the third dielectric proton layer is 3-8 nm, the thickness of the fourth dielectric proton layer is 290-310 nm, the thickness of the fifth dielectric proton layer is 590-610, the thickness of the sixth dielectric proton layer is 490-510 nm, and the thickness of the seventh dielectric proton layer is 690-710 nm. In another aspect, a transistor is provided that includes a channel layer, a barrier layer, a first dielectric layer, a first metal layer, a second dielectric layer, and a second metal layer; The channel layer, the barrier layer, the first dielectric layer, the first metal layer, the second dielectric layer and the second metal layer are sequentially laminated; The second dielectric layer is a Si compound layer manufactured by adopting a plasma energy gradient increasing PECVD process. Optionally, the thickness of the second dielectric layer is 700-4000 nm. Optionally, the first dielectric layer includes a first dielectric