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CN-122002836-A - Circuit design-process collaborative optimization method, preparation method and circuit

CN122002836ACN 122002836 ACN122002836 ACN 122002836ACN-122002836-A

Abstract

The invention provides a circuit design-process collaborative optimization method, a preparation method and a circuit based on an edge contact two-dimensional transistor, which are used for remarkably improving the load linearity, output resistance and switching stability of the two-dimensional transistor by adopting an edge contact process and optimizing the geometric parameters of the transistor according to the performance requirement of an analog circuit. The method specifically comprises the steps of optimizing design of the edge contact transistor, representing and improving load performance, and integrating and applying the system in the high-performance analog circuit module. The invention provides a complete solution from transistor-level process optimization to circuit-level performance improvement, and provides a key technical path for designing and manufacturing the high-linearity and high-stability analog and mixed-signal integrated circuit based on the novel two-dimensional semiconductor.

Inventors

  • BAO WENZHONG

Assignees

  • 原集微(上海)电子有限公司

Dates

Publication Date
20260508
Application Date
20260407

Claims (15)

  1. 1. The circuit design-process collaborative optimization method based on the edge contact two-dimensional transistor is characterized by at least comprising the following steps of: Performing collaborative optimization on a circuit where the edge contact two-dimensional transistor is located in a process layer and a design layer, and determining the size and process parameters of the device after collaborative optimization so that the performance of the edge contact two-dimensional transistor meets application requirements; in the process level, optimizing the edge contact process of the edge contact two-dimensional transistor based on the requirement of the edge contact two-dimensional transistor and/or a circuit where the edge contact two-dimensional transistor is positioned; And optimizing the geometric parameters of the edge contact two-dimensional transistor based on the edge contact two-dimensional transistor and/or the performance index of a circuit where the edge contact two-dimensional transistor is positioned in a design level.
  2. 2. The method of claim 1, wherein the optimized process comprises at least one of depth, thickness, width, length, and process.
  3. 3. The circuit design-process collaborative optimization method based on an edge-contacted two-dimensional transistor according to claim 1, wherein when the performance index is a load factor of the edge-contacted two-dimensional transistor, geometry parameters of the edge-contacted two-dimensional transistor are optimized so that the edge-contacted two-dimensional transistor is close to an ideal current source.
  4. 4. The method for collaborative optimization of edge-contact two-dimensional transistor based circuit design-process according to any one of claims 1-3 further comprising applying collaborative optimized edge-contact two-dimensional transistors to analog portions of the circuit and applying hybrid or top-contact two-dimensional transistors to digital portions of the circuit.
  5. 5. A method for manufacturing an edge-contacted two-dimensional transistor, which is optimized based on the circuit design-process collaborative optimization method based on the edge-contacted two-dimensional transistor according to any one of claims 1-4, and is characterized in that the method for manufacturing the edge-contacted two-dimensional transistor at least comprises the following steps: s11) providing a substrate, forming a two-dimensional semiconductor material layer on the substrate; S12) patterning the two-dimensional semiconductor material layer to form a source-drain region, and forming a source-drain metal electrode with edge contact on the side surface of the two-dimensional semiconductor material layer; S13) forming a gate structure on the structure obtained in step S12).
  6. 6. The method for manufacturing an edge-contact two-dimensional transistor according to claim 5, wherein the step S12) comprises: S121) defining a source drain region, etching a two-dimensional semiconductor material layer of the source drain region to pattern the two-dimensional semiconductor material layer and expose the side surface of the two-dimensional semiconductor material layer; s122) cleaning the side surface of the two-dimensional semiconductor material layer by plasma treatment; s123) depositing electrode materials in the source and drain regions at two sides of the two-dimensional semiconductor material layer.
  7. 7. The method of manufacturing an edge-contact two-dimensional transistor according to any one of claims 5-6, wherein the gate structure is a top gate structure.
  8. 8. The method of manufacturing an edge-contact two-dimensional transistor according to any one of claims 5 to 6, wherein the two-dimensional semiconductor material layer is a transition metal chalcogenide thin film manufactured by chemical vapor deposition, atomic layer deposition or transfer method.
  9. 9. The method of manufacturing an edge-contact two-dimensional transistor according to any one of claims 5 to 6, further comprising a post-annealing step after the transistor manufacturing is completed in step 3).
  10. 10. A circuit, the circuit comprising at least: An analog circuit module comprising the edge-contact two-dimensional transistor obtained by optimizing the circuit design-process collaborative optimization method based on the edge-contact two-dimensional transistor according to any one of claims 1 to 4.
  11. 11. The circuit of claim 10, wherein the analog circuit block comprises at least one of an operational amplifier, a comparator, and a sample-and-hold circuit.
  12. 12. The circuit of claim 10, wherein the edge-contacted two-dimensional transistor acts as a load tube for an inverter in the analog circuit module.
  13. 13. The circuit of claim 10, wherein the edge-contacted two-dimensional transistor acts as a gain stage for a discrete-time comparator in the analog circuit block.
  14. 14. The circuit according to any one of claims 10-13, characterized in that the circuit further comprises a digital circuit module comprising hybrid contact two-dimensional transistors and/or top contact two-dimensional transistors.
  15. 15. The circuit of claim 14, wherein the circuit is an analog-to-digital converter comprising a voltage divider network, a sample-and-hold module, a comparator array, and an encoder; The voltage dividing network divides the reference voltage; The sampling and holding module samples the input voltage to obtain a sampling signal, wherein the analog switch adopts the edge contact two-dimensional transistor; The comparator array compares the sampling signal with each reference provided by the voltage division network and outputs a comparison result, wherein a load tube of a first-stage inverter of each comparator adopts the edge contact two-dimensional transistor; the encoder generates an encoded signal based on each comparison result output by the comparator array, including a hybrid contact two-dimensional transistor and/or a top contact two-dimensional transistor.

Description

Circuit design-process collaborative optimization method, preparation method and circuit Technical Field The invention relates to the technical field of semiconductor device and integrated circuit design, in particular to a circuit design-process collaborative optimization method, a preparation method and a circuit based on an edge contact two-dimensional transistor. Background With the rapid development of the internet of things, wearable equipment and intelligent sensing systems, the requirements for an analog front-end circuit with low power consumption, high linearity and high stability are increasingly urgent. Conventional silicon-based cmos technology, while dominant in digital circuits, is often limited by challenges in terms of power consumption, body effects, and compatibility with flexibility, heterogeneous integration, etc., in analog circuits facing the above applications. In recent years, two-dimensional transition metal chalcogenide (such as MoS 2, WS2) semiconductor materials are ideal candidates for constructing next-generation high-performance and low-power-consumption analog integrated circuits due to their atomic thickness, dangling bond free surface, excellent static control capability and potential for compatibility with subsequent processes. However, successful application of two-dimensional semiconductor materials to analog circuits still presents significant challenges. Analog circuits are extremely sensitive to transistor performance parameters such as transconductance linearity, output resistance, noise, and stability. Among these, the metal-semiconductor contact resistance and the quality of the contact interface are key factors affecting the two-dimensional transistor performance, especially the driving capability and linearity. The conventional top contact structure forms a schottky barrier on the surface of a two-dimensional material, which often results in a larger contact resistance and non-ideal transmission characteristics, and limits the application of the top contact structure in a processing circuit requiring high-precision analog signals. Therefore, how to successfully apply the two-dimensional semiconductor material to the analog circuit to exert the advantages of the two-dimensional semiconductor material in the analog circuit has become one of the problems to be solved by those skilled in the art. It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present invention and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the invention section. Disclosure of Invention In view of the above-mentioned drawbacks of the prior art, the present invention aims to provide a circuit design-process collaborative optimization method, a manufacturing method and a circuit based on an edge contact two-dimensional transistor, which are used for solving the problem that two-dimensional semiconductor materials cannot be applied to analog circuits in the prior art. To achieve the above and other related objects, the present invention provides a circuit design-process collaborative optimization method based on an edge contact two-dimensional transistor, which at least comprises: Performing collaborative optimization on a circuit where the edge contact two-dimensional transistor is located in a process layer and a design layer, and determining the size and process parameters of the device after collaborative optimization so that the performance of the edge contact two-dimensional transistor meets application requirements; in the process level, optimizing the edge contact process of the edge contact two-dimensional transistor based on the requirement of the edge contact two-dimensional transistor and/or a circuit where the edge contact two-dimensional transistor is positioned; And optimizing the geometric parameters of the edge contact two-dimensional transistor based on the edge contact two-dimensional transistor and/or the performance index of a circuit where the edge contact two-dimensional transistor is positioned in a design level. Optionally, the optimized manufacturing process includes at least one of depth, thickness, width, length, and treatment process. Optionally, when the performance index is a load factor of the edge-contacted two-dimensional transistor, the geometric parameter of the edge-contacted two-dimensional transistor is optimized so that the edge-contacted two-dimensional transistor is close to an ideal current source. More optionally, the circuit design-process collaborative optimization method based on the edge contact two-dimensional transistor further comprises the steps of applying the edge contact two-dimensional transistor obtained through collaborative optimization t