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CN-122002838-A - Transistor and manufacturing method thereof

CN122002838ACN 122002838 ACN122002838 ACN 122002838ACN-122002838-A

Abstract

The present disclosure provides a transistor and a method of fabricating the same. The transistor comprises a superlattice structure, a first dielectric layer, a source electrode, a drain electrode and a fin-type grid electrode, wherein the superlattice structure comprises a plurality of channel layers and barrier layers which are alternately stacked periodically, the superlattice structure comprises two first grooves, a plurality of second grooves and a third groove, the source electrode and the drain electrode are located on two opposite sides of the top surface of the superlattice structure in a first direction a and are respectively inserted into the two first grooves, the first dielectric layer covers the top surface of the superlattice structure, the plurality of second grooves and the third groove, the fin-type grid electrode is located on the first dielectric layer and is respectively inserted into the plurality of second grooves, the opening of the third groove is located on the top surface of the superlattice structure, the bottom of the third groove is located in the channel layer closest to the top surface of the superlattice structure, the third groove is located between the fin-type grid electrode and the drain electrode, the second direction b penetrates the superlattice structure, and the second direction b intersects the first direction a.

Inventors

  • Chen Kuangli
  • WANG RUI
  • YANG YING
  • YANG TING

Assignees

  • 京东方华灿光电(广东)有限公司

Dates

Publication Date
20260508
Application Date
20251216

Claims (10)

  1. 1. A transistor is characterized by comprising a superlattice structure (101), a first dielectric layer (102), a source electrode (103), a drain electrode (104) and a fin-type gate electrode (105), wherein the superlattice structure (101) comprises a plurality of channel layers (111) and barrier layers (112) which are alternately stacked in a periodic manner; The superlattice structure (101) comprises two first grooves (110), a plurality of second grooves (120) and a third groove (130), wherein the source electrode (103) and the drain electrode (104) are positioned on two opposite sides of the top surface of the superlattice structure (101) in a first direction a and are respectively inserted into the two first grooves (110), the first dielectric layer (102) covers the top surface of the superlattice structure (101), the plurality of second grooves (120) and the third groove (130), and the fin grid (105) is positioned on the first dielectric layer (102) and is respectively inserted into the plurality of second grooves (120); The opening of the third groove (130) is located on the top surface of the superlattice structure (101), the bottom of the third groove (130) is located in the channel layer (111) closest to the top surface of the superlattice structure (101), the third groove (130) is located between the fin gate (105) and the drain (104) and penetrates the superlattice structure (101) along a second direction b, and the second direction b is intersected with the first direction a.
  2. 2. The transistor according to claim 1, wherein the width w of the third recess (130) in the first direction a is 0.5-5 micrometers.
  3. 3. The transistor of claim 1, wherein the depth h of the third recess (130) at the portion of the channel layer (111) closest to the top surface of the superlattice structure (101) is 1/3-2/3 of the thickness of the channel layer (111) closest to the top surface of the superlattice structure (101).
  4. 4. A transistor according to any of claims 1to 3, characterized in that the transistor further comprises a cap layer (106) and a second dielectric layer (107), the cap layer (106) and the second dielectric layer (107) being sequentially stacked between the superlattice structure (101) and the first dielectric layer (102); The first groove (110), the second groove (120) and the third groove (130) all penetrate through the cap layer (106), the first groove (110) and the second groove (120) all penetrate through the second dielectric layer (107), and the second dielectric layer (107) covers the third groove (130).
  5. 5. A transistor according to any of claims 1 to 3, characterized in that the superlattice structure (101) comprises 2-5 periods of alternating layers of the channel layer (111) and the barrier layer (112).
  6. 6. A method of fabricating a transistor, the method comprising: fabricating a superlattice structure, the superlattice structure including a plurality of channel layers and barrier layers alternately stacked in cycles; Forming two first grooves, a plurality of second grooves and a third groove in the superlattice structure, wherein an opening of the third groove is positioned on the top surface of the superlattice structure, and the bottom of the third groove is positioned in the channel layer closest to the top surface of the superlattice structure; Manufacturing a source electrode and a drain electrode which are positioned on two opposite sides of the top surface of the superlattice structure in the first direction a and are respectively inserted into the two first grooves; Manufacturing a first dielectric layer on the superlattice structure, wherein the first dielectric layer covers the top surface of the superlattice structure, the plurality of second grooves and the third grooves; and manufacturing a fin-type grid electrode, wherein the fin-type grid electrode is positioned on the first dielectric layer and is respectively inserted into the second grooves, the third groove is positioned between the fin-type grid electrode and the drain electrode and penetrates through the superlattice structure along a second direction b, and the second direction b is intersected with the first direction a.
  7. 7. The method of claim 6, wherein the third grooves have a width w of 0.5-5 microns in the first direction a.
  8. 8. The method of claim 6 wherein the depth h of the third recess in the portion of the channel layer closest to the top surface of the superlattice structure is 1/3 to 2/3 of the thickness of the channel layer closest to the top surface of the superlattice structure.
  9. 9. The method according to any one of claims 6 to 8, further comprising: Sequentially manufacturing a cap layer and a second dielectric layer, wherein the cap layer and the second dielectric layer are sequentially laminated between the superlattice structure and the first dielectric layer; after the cap layer is manufactured, manufacturing the third groove before the second dielectric layer is manufactured; and after the second dielectric layer is manufactured, manufacturing the first groove and the second groove before the first dielectric layer is manufactured.
  10. 10. The method of any one of claims 6 to 8, wherein the superlattice structure includes the channel layer and the barrier layer alternately stacked in 2-5 cycles.

Description

Transistor and manufacturing method thereof Technical Field The present disclosure relates to the field of semiconductor devices, and more particularly, to a transistor and a method of fabricating the same. Background GaN-based transistors are candidates for next generation power switching applications due to their excellent device characteristics (low specific on-resistance, low switching loss, and high breakdown voltage). Multi-channel transistors have received attention in recent years as an extended form of high electron mobility transistor (High Electron Mobility Transistor, HEMT) structure. The main characteristic of the multi-channel transistor is that a plurality of parallel two-dimensional electron gas (2 DEG) channels are introduced through a multi-layer stacked structure of AlGaN/GaN heterojunction. However, the current multi-channel transistor faces many technical challenges, such as a fin gate structure, in which multiple channels are controlled by a top gate and a side gate, and different channels are conducted and not synchronized due to different control degrees, so that transconductance performance of the transistor is limited. Disclosure of Invention The embodiment of the disclosure provides a transistor and a manufacturing method thereof, which can improve the transconductance performance of the transistor. The technical scheme is as follows: In one aspect, a transistor is provided that includes a superlattice structure including a plurality of periodically alternating stacked channel layers and barrier layers, a first dielectric layer, a source, a drain, and a fin gate; The superlattice structure comprises two first grooves, a plurality of second grooves and a third groove; the source electrode and the drain electrode are positioned on two opposite sides of the top surface of the superlattice structure in the first direction a, and are respectively inserted into the two first grooves; the first dielectric layer covers the top surface of the superlattice structure, the plurality of second grooves and the third grooves; the fin-type grid electrode is positioned on the first dielectric layer and is respectively inserted into the plurality of second grooves; The opening of the third groove is positioned on the top surface of the superlattice structure, the bottom of the third groove is positioned in the channel layer closest to the top surface of the superlattice structure, the third groove is positioned between the fin gate and the drain electrode and penetrates through the superlattice structure along a second direction b, and the second direction b is intersected with the first direction a. Optionally, in the first direction a, a width w of the third groove is 0.5-5 micrometers. Optionally, the depth h of the third groove at the channel layer part closest to the top surface of the superlattice structure is 1/3-2/3 of the thickness of the channel layer closest to the top surface of the superlattice structure. Optionally, the transistor further includes a cap layer and a second dielectric layer, where the cap layer and the second dielectric layer are sequentially stacked between the superlattice structure and the first dielectric layer; The first groove, the second groove and the third groove all penetrate through the cap layer, the first groove and the second groove all penetrate through the second dielectric layer, and the second dielectric layer covers the third groove. Optionally, the superlattice structure includes the channel layer and the barrier layer alternately stacked in 2-5 periods. In another aspect, a method for fabricating a transistor is provided, the method comprising: fabricating a superlattice structure, the superlattice structure including a plurality of channel layers and barrier layers alternately stacked in cycles; Forming two first grooves, a plurality of second grooves and a third groove in the superlattice structure, wherein an opening of the third groove is positioned on the top surface of the superlattice structure, and the bottom of the third groove is positioned in the channel layer closest to the top surface of the superlattice structure; Manufacturing a source electrode and a drain electrode which are positioned on two opposite sides of the top surface of the superlattice structure in the first direction a and are respectively inserted into the two first grooves; Manufacturing a first dielectric layer on the superlattice structure, wherein the first dielectric layer covers the top surface of the superlattice structure, the plurality of second grooves and the third grooves; and manufacturing a fin-type grid electrode, wherein the fin-type grid electrode is positioned on the first dielectric layer and is respectively inserted into the second grooves, the third groove is positioned between the fin-type grid electrode and the drain electrode and penetrates through the superlattice structure along a second direction b, and the second direction b is intersected wit