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CN-122002839-A - Transistor and manufacturing method thereof

CN122002839ACN 122002839 ACN122002839 ACN 122002839ACN-122002839-A

Abstract

The present disclosure provides a transistor and a method of fabricating the same. The transistor comprises a superlattice structure, a gate insulating layer, a source electrode, a drain electrode and a fin-type gate electrode, wherein the superlattice structure comprises a plurality of channel layers and barrier layers which are alternately stacked periodically, the superlattice structure comprises two first grooves and a plurality of second grooves, openings of the first grooves and the second grooves are located on the top surface of the superlattice structure, bottoms of the first grooves and the second grooves are located in the channel layers closest to the bottom surface of the superlattice structure, the two first grooves are located on two opposite sides of the top surface of the superlattice structure in a first direction a, the plurality of second grooves are located between the two first grooves and are distributed at intervals along a second direction b, the first direction a is intersected with the second direction b, the lengths of the two adjacent second grooves are different in the first direction a, and the minimum distances between the two adjacent second grooves and the drain electrode are different.

Inventors

  • Chen Kuangli
  • ZHANG ZHONGYU
  • JIANG ZHULIN

Assignees

  • 京东方华灿光电(广东)有限公司

Dates

Publication Date
20260508
Application Date
20251216

Claims (10)

  1. 1. A transistor is characterized by comprising a superlattice structure (101), a gate insulating layer (102), a source electrode (103), a drain electrode (104) and a fin gate electrode (105), wherein the superlattice structure (101) comprises a plurality of channel layers (111) and barrier layers (112) which are alternately stacked in a periodic manner; The superlattice structure (101) comprises two first grooves (110) and a plurality of second grooves (120), wherein openings of the first grooves (110) and the second grooves (120) are positioned on the top surface of the superlattice structure (101), and bottoms of the first grooves (110) and the second grooves (120) are positioned in the channel layer (111) closest to the bottom surface of the superlattice structure (101); The two first grooves (110) are positioned on two opposite sides of the top surface of the superlattice structure (101) in a first direction a, the plurality of second grooves (120) are positioned between the two first grooves (110) and are arranged at intervals along a second direction b, and the first direction a and the second direction b are intersected; The source electrode (103) and the drain electrode (104) are respectively inserted into the two first grooves (110), the grid insulation layer (102) covers the top surface of the superlattice structure (101) and the plurality of second grooves (120), and the fin grid (105) is positioned on the grid insulation layer (102) and is respectively inserted into the plurality of second grooves (120); in the first direction a, lengths of two adjacent second grooves (120) are different, and minimum distances between the two adjacent second grooves (120) and the drain electrode (104) are different.
  2. 2. The transistor of claim 1, wherein in the second direction b, a minimum distance of the plurality of second grooves (120) from the drain electrode (104) alternates according to a first distance and a second distance, the first distance being greater than the second distance.
  3. 3. The transistor of claim 1, wherein in the second direction b, a minimum distance of the plurality of second recesses (120) from the drain (104) varies in a decreasing followed by increasing manner.
  4. 4. A transistor according to any of claims 1 to 3, characterized in that the difference between the smallest distances between two adjacent second recesses (120) and the drain (104) is 0.1-1 micrometer.
  5. 5. A transistor according to any of claims 1 to 3, characterized in that in the first direction a, the smallest distance between two adjacent second recesses (120) and the source (103) is the same.
  6. 6. A method of fabricating a transistor, the method comprising: fabricating a superlattice structure, the superlattice structure including a plurality of channel layers and barrier layers alternately stacked in cycles; Forming two first grooves and a plurality of second grooves in the superlattice structure, wherein openings of the first grooves and the second grooves are positioned on the top surface of the superlattice structure, bottoms of the first grooves and the second grooves are positioned in the channel layer closest to the bottom surface of the superlattice structure, the two first grooves are positioned on two opposite sides of the top surface of the superlattice structure in a first direction a, the plurality of second grooves are positioned between the two first grooves and are distributed at intervals along a second direction b, and the first direction a is intersected with the second direction b; Manufacturing a source electrode and a drain electrode, wherein the source electrode and the drain electrode are respectively inserted into the two first grooves, the lengths of two adjacent second grooves are different in the first direction a, and the minimum distances between the two adjacent second grooves and the drain electrode are different; Manufacturing a gate insulating layer on the superlattice structure, wherein the gate insulating layer covers the top surface of the superlattice structure and the second grooves; and manufacturing fin-type gates, wherein the fin-type gates are positioned on the gate insulation layer and are respectively inserted into the second grooves.
  7. 7. The method of claim 6, wherein a minimum distance of the plurality of second grooves from the drain electrode in the second direction b alternates with a first distance and a second distance, the first distance being greater than the second distance.
  8. 8. The method of claim 6, wherein in the second direction b, a minimum distance of the plurality of second grooves from the drain electrode varies in a decreasing-then-increasing manner.
  9. 9. The method according to any one of claims 6 to 8, wherein a difference between minimum distances between adjacent two of the second grooves and the drain electrode is 0.1 to 1 μm.
  10. 10. A method according to any one of claims 6 to 8, characterized in that in the first direction a, the smallest distance between two adjacent second recesses and the source is the same.

Description

Transistor and manufacturing method thereof Technical Field The present disclosure relates to the field of semiconductor devices, and more particularly, to a transistor and a method of fabricating the same. Background GaN-based transistors are candidates for next generation power switching applications due to their excellent device characteristics (low specific on-resistance, low switching loss, and high breakdown voltage). Multi-channel transistors have received attention in recent years as an extended form of high electron mobility transistor (High Electron Mobility Transistor, HEMT) structure. The main characteristic of the multi-channel transistor is that a plurality of parallel two-dimensional electron gas (2 DEG) channels are introduced through a multi-layer stacked structure of AlGaN/GaN heterojunction. However, the present multi-channel transistor faces many technical challenges, such as a fin gate structure, and how to improve the voltage resistance of the multi-channel transistor is a current challenge. Disclosure of Invention The embodiment of the disclosure provides a transistor and a manufacturing method thereof, which can improve the voltage resistance of a multi-channel transistor. The technical scheme is as follows: In one aspect, a transistor is provided that includes a superlattice structure including a plurality of periodically alternating stacked channel layers and barrier layers, a gate insulating layer, a source, a drain, and a fin gate; The superlattice structure comprises two first grooves and a plurality of second grooves, wherein openings of the first grooves and the second grooves are positioned on the top surface of the superlattice structure, and bottoms of the first grooves and the second grooves are positioned in the channel layer closest to the bottom surface of the superlattice structure; The two first grooves are positioned on two opposite sides of the top surface of the superlattice structure in a first direction a, the plurality of second grooves are positioned between the two first grooves and are arranged at intervals along a second direction b, and the first direction a and the second direction b are intersected; The source electrode and the drain electrode are respectively inserted into the two first grooves; the gate insulating layer covers the top surface of the superlattice structure and the plurality of second grooves; the fin-type grid electrode is positioned on the grid insulation layer and is respectively inserted into the second grooves; in the first direction a, lengths of two adjacent second grooves are different, and minimum distances between the two adjacent second grooves and the drain electrode are different. Optionally, in the second direction b, a minimum distance between the plurality of second grooves and the drain electrode is alternately changed according to a first distance and a second distance, and the first distance is greater than the second distance. Optionally, in the second direction b, a minimum distance between the plurality of second grooves and the drain electrode varies in a manner of decreasing before increasing. Optionally, the difference between the minimum distances between two adjacent second grooves and the drain electrode is 0.1-1 micrometer. Optionally, in the first direction a, the minimum distance between two adjacent second grooves and the source electrode is the same. In another aspect, a method for fabricating a transistor is provided, the method comprising: fabricating a superlattice structure, the superlattice structure including a plurality of channel layers and barrier layers alternately stacked in cycles; Forming two first grooves and a plurality of second grooves in the superlattice structure, wherein openings of the first grooves and the second grooves are positioned on the top surface of the superlattice structure, bottoms of the first grooves and the second grooves are positioned in the channel layer closest to the bottom surface of the superlattice structure, the two first grooves are positioned on two opposite sides of the top surface of the superlattice structure in a first direction a, the plurality of second grooves are positioned between the two first grooves and are distributed at intervals along a second direction b, and the first direction a is intersected with the second direction b; Manufacturing a source electrode and a drain electrode, wherein the source electrode and the drain electrode are respectively inserted into the two first grooves, the lengths of two adjacent second grooves are different in the first direction a, and the minimum distances between the two adjacent second grooves and the drain electrode are different; Manufacturing a gate insulating layer on the superlattice structure, wherein the gate insulating layer covers the top surface of the superlattice structure and the second grooves; and manufacturing fin-type gates, wherein the fin-type gates are positioned on the gate insulation la