Search

CN-122002840-A - High electron mobility transistor chip and preparation method thereof

CN122002840ACN 122002840 ACN122002840 ACN 122002840ACN-122002840-A

Abstract

The invention discloses a transistor chip with high electron mobility and a preparation method thereof, belonging to the technical field of semiconductors. The high electron mobility transistor chip comprises a substrate, and an alternate polarization layer, a first buffer layer, a second buffer layer, a channel layer, a barrier layer, a super junction layer and a cap layer which are sequentially stacked on the substrate, wherein the alternate polarization layer comprises a GaN layer and an AlGaN layer which are periodically and alternately stacked to form a superlattice structure, the first buffer layer is a GaN layer, the second buffer layer is a C-doped GaN layer, and the C doping concentration of the second buffer layer is gradually increased along the epitaxial growth direction. The embodiment of the disclosure can effectively simplify the structure process and reduce the preparation cost.

Inventors

  • GU WENXIA
  • WANG JUNNAN
  • GUO LILI

Assignees

  • 京东方华灿光电(浙江)有限公司

Dates

Publication Date
20260508
Application Date
20251218

Claims (10)

  1. 1. A high electron mobility transistor chip, comprising a substrate (10), and alternating polarization layers (20), a first buffer layer (30), a second buffer layer (40), a channel layer (50), a barrier layer (60), a super junction layer (70) and a cap layer (80) stacked in sequence on the substrate (10); the alternate polarization layer (20) comprises a GaN layer and an AlGaN layer which are periodically and alternately stacked to form a superlattice structure; The first buffer layer (30) is a GaN layer; the second buffer layer (40) is a C-doped GaN layer, and the C-doping concentration of the second buffer layer (40) is gradually increased along the epitaxial growth direction.
  2. 2. The hemt chip according to claim 1, wherein in the alternate polarization layer (20), an Al composition of the AlGaN layer is 5% -15%, a number of repetition cycles of the GaN layer and the AlGaN layer is 15-25, and a thickness of the GaN layer and the AlGaN layer for each repetition cycle is 15-25 nm.
  3. 3. The hemt chip of claim 1, wherein the second buffer layer (40) has a C-doping concentration of 1e 18-5 e19cm -3 , the C-doping concentration of the second buffer layer (40) increasing once every 50-150 nm in the epitaxial growth direction.
  4. 4. The hemt chip of claim 1, wherein the hemt chip comprises a first electrode (910) and a plurality of second electrodes (920); The first electrode (910) is connected with the barrier layer (60), and the first electrode (910) is of a continuous zigzag structure extending along a first direction so as to form a plurality of adjacently arranged grooves (911) in the first electrode (910), wherein the first direction is perpendicular to the epitaxial growth direction; The second electrode (920) is connected with the cap layer (80), one of the second electrodes (920) is positioned in one groove (911), and the second electrode (920) is spaced from the groove wall of the corresponding groove (911).
  5. 5. The hemt chip according to claim 4, wherein the super junction layer (70) is provided in the recess (911), and a distance between the super junction layer (70) and a wall of the recess (911) in the first direction is 2-4 μm.
  6. 6. The hemt chip of claim 4, wherein both sides of said super junction layer (70) have groove walls of said groove (911) in said first direction, and a distance between said super junction layer (70) and groove walls of said groove (911) on both sides is the same.
  7. 7. The hemt chip of claim 4, wherein said second electrode (920) and said first electrode (910) comprise a first Ti layer, an Al layer and a second Ti layer stacked in sequence; The thickness of the first Ti layer is 10-50 nm; the thickness of the Al layer is 100-500 nm; The thickness of the second Ti layer is 50-150 nm.
  8. 8. The hemt chip of claim 4, wherein said super junction layer (70) has a width of 20-30 μm in said first direction.
  9. 9. A method for preparing a transistor chip with high electron mobility is characterized in that, the preparation method is used for preparing the high electron mobility transistor chip according to any one of claims 1 to 8, and comprises the following steps: Providing a substrate (10); Preparing an alternate polarization layer (20) on one side of the substrate (10), wherein the alternate polarization layer (20) comprises a GaN layer and an AlGaN layer which are periodically and alternately stacked to form a superlattice structure; Preparing a first buffer layer (30) on one side of the alternate polarization layer (20), wherein the first buffer layer (30) is a GaN layer; Preparing a second buffer layer (40) on one side of the first buffer layer (30), wherein the second buffer layer (40) is a C-doped GaN layer, and the C-doped concentration of the second buffer layer (40) is gradually increased along the epitaxial growth direction; and preparing a channel layer (50), a barrier layer (60), a super junction layer (70) and a cap layer (80) on one side of the second buffer layer (40) in sequence.
  10. 10. The method of manufacturing according to claim 9, characterized in that the preparation of the alternating polarization layer (20) on one side of the substrate (10) comprises: setting the number of repetition periods to 15-25, and setting the thickness of each repetition period to 15-25 nm; And setting the Al component of the AlGaN layer to be 5% -15%.

Description

High electron mobility transistor chip and preparation method thereof Technical Field The present disclosure relates to the field of semiconductor technology, and in particular, to a high electron mobility transistor die and a method for manufacturing the same. Background HEMTs (High Electron Mobility Transistor, high electron mobility transistors) are a type of heterojunction field effect transistor. In the related art, the silicon-based superjunction device realizes charge balance through alternately arranged P/N type columns, thereby remarkably reducing on-resistance, improving breakdown voltage and improving switching speed. However, the structure process in the above related art is complicated and the manufacturing cost is high. Disclosure of Invention The embodiment of the disclosure provides a high electron mobility transistor chip and a preparation method thereof, which can effectively simplify the structure process and reduce the preparation cost. The technical scheme is as follows: in one aspect, an embodiment of the present disclosure provides a high electron mobility transistor chip, including a substrate, and an alternating polarization layer, a first buffer layer, a second buffer layer, a channel layer, a barrier layer, a super junction layer, and a cap layer sequentially stacked on the substrate; The alternate polarization layers comprise GaN layers and AlGaN layers which are alternately stacked periodically to form a superlattice structure; The first buffer layer is a GaN layer; The second buffer layer is a C-doped GaN layer, and the C-doped concentration of the second buffer layer is gradually increased along the epitaxial growth direction. In one implementation of the disclosure, in the alternate polarization layers, an Al component of the AlGaN layer is 5% -15%, a number of repetition cycles of the GaN layer and the AlGaN layer is 15% -25, and thicknesses of the GaN layer and the AlGaN layer in each repetition cycle are 15% -25 nm. In one implementation of the disclosure, the C-doping concentration of the second buffer layer is 1e 18-5 e19cm -3, and the C-doping concentration of the second buffer layer is increased once every 50-150 nm in the epitaxial growth direction. In one implementation of the present disclosure, a high electron mobility transistor die includes a first electrode and a plurality of second electrodes; The first electrode is connected with the barrier layer, and is of a continuous zigzag structure extending along a first direction so as to form a plurality of adjacently arranged grooves in the first electrode, wherein the first direction is perpendicular to the epitaxial growth direction; The second electrode is connected with the cap layer, one of the second electrodes is positioned in one groove, and the second electrode is spaced from the wall of the corresponding groove. In one implementation manner of the present disclosure, the super junction layer is disposed in the groove, and in the first direction, a distance between the super junction layer and a groove wall of the groove is 2-4 μm. In one implementation of the disclosure, in the first direction, both sides of the super junction layer have groove walls of the grooves, and a distance between the super junction layer and the groove walls of the grooves on both sides is the same. In one implementation of the disclosure, the second electrode and the first electrode include a first Ti layer, an Al layer, and a second Ti layer stacked in order; The thickness of the first Ti layer is 10-50 nm; the thickness of the Al layer is 100-500 nm; The thickness of the second Ti layer is 50-150 nm. In one implementation of the disclosure, in the first direction, the width of the super junction layer is 20-30 μm. In another aspect, an embodiment of the present disclosure provides a method for preparing a high electron mobility transistor chip, where the method includes: Providing a substrate; Preparing an alternate polarization layer on one side of the substrate, wherein the alternate polarization layer comprises a GaN layer and an AlGaN layer which are periodically and alternately stacked to form a superlattice structure; Preparing a first buffer layer on one side of the alternate polarization layer, wherein the first buffer layer is a GaN layer; Preparing a second buffer layer on one side of the first buffer layer, wherein the second buffer layer is a C-doped GaN layer, and the C-doped concentration of the second buffer layer is gradually increased along the epitaxial growth direction; and preparing a channel layer, a barrier layer, a super junction layer and a cap layer on one side of the second buffer layer in sequence. In one implementation of the present disclosure, preparing an alternating polarization layer on one side of the substrate includes: setting the number of repetition periods to 15-25, and setting the thickness of each repetition period to 15-25 nm; And setting the Al component of the AlGaN layer to be 5% -15%