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CN-122002841-A - Bidirectional-conduction transistor and preparation method thereof

CN122002841ACN 122002841 ACN122002841 ACN 122002841ACN-122002841-A

Abstract

The disclosure provides a transistor with bidirectional conduction and a preparation method thereof, and belongs to the field of power electronics. The transistor comprises a substrate, a semiconductor multilayer body, a first electrode, a second electrode, a first grid control structure and a second grid control structure, wherein the semiconductor multilayer body is positioned on the surface of the substrate, the first electrode, the first grid control structure, the second grid control structure and the second electrode are sequentially arranged on the semiconductor multilayer body at intervals along the same direction, the first grid control structure and the second grid control structure comprise a p-type layer and a grid electrode, and the p-type layer and the grid electrode are sequentially laminated on the semiconductor multilayer body. The embodiment of the disclosure can realize bidirectional conduction of the transistor and reduce the complexity of circuit layout.

Inventors

  • WANG JUNNAN
  • WANG YILEI
  • SUN JIAN

Assignees

  • 京东方华灿光电(广东)有限公司

Dates

Publication Date
20260508
Application Date
20251219

Claims (10)

  1. 1. A transistor, characterized in that the transistor comprises a substrate (10), a semiconductor multilayer body (20), a first electrode (31), a second electrode (32) and a gate control structure (4), the semiconductor multilayer body (20) being located on a surface of the substrate (10); The grid control structure (4) comprises a first grid control structure (4 a) and a second grid control structure (4 b); the first electrode (31), the first grid control structure (4 a), the second grid control structure (4 b) and the second electrode (32) are sequentially arranged on the semiconductor multilayer body (20) at intervals along the same direction; The first gate control structure (4 a) and the second gate control structure (4 b) comprise a p-type layer (41) and a gate (42), and the p-type layer (41) and the gate (42) are sequentially laminated on the semiconductor multilayer body (20).
  2. 2. The transistor of claim 1, further comprising a first layer of semiconductor material (50), the first layer of semiconductor material (50) being located between the semiconductor multilayer body (20) and the gate structure (4), the first layer of semiconductor material (50) comprising a first stripe (51), a second stripe (52), and a grid (53) connecting the first stripe (51) and the second stripe (52).
  3. 3. The transistor according to claim 2, characterized in that the first stripe (51) is located between the first gate structure (4 a) and the semiconductor multilayer body (20), and the second stripe (52) is located between the second gate structure (4 b) and the semiconductor multilayer body (20).
  4. 4. A transistor according to claim 3, wherein the grid portion (53) includes a plurality of third stripe portions (531) and a plurality of fourth stripe portions (532), the plurality of third stripe portions (531) being arranged on the semiconductor multilayer body (20) at intervals along a first direction (1 a), the first direction (1 a) being an arrangement direction of the first electrode (31), the first gate control structure (4 a), the second gate control structure (4 b) and the second electrode (32); The fourth strip-shaped parts (532) are arranged on the semiconductor multilayer body (20) at intervals along a second direction (1 b), the second direction (1 b) is intersected with the first direction (1 a), and the third strip-shaped parts (531) are intersected with each fourth strip-shaped part (532).
  5. 5. The transistor of claim 4, wherein each of the fourth strips (532) comprises a first end and a second end, the first end being connected to the first strip (51) and the second end being connected to the second strip (52).
  6. 6. A transistor according to any of claims 2 to 5, characterized in that the first semiconductor material layer (50) comprises a u-type GaN layer.
  7. 7. A transistor according to any of claims 2 to 5, characterized in that the p-type layer (41) comprises a first p-type GaN layer (411) and a second p-type GaN layer (412) stacked in sequence, the doping concentration of the first p-type GaN layer (411) being lower than the doping concentration of the second p-type GaN layer (412).
  8. 8. The transistor according to claim 7, characterized in that the orthographic projection of the second p-type GaN layer (412) on the substrate (10) is located within the orthographic projection of the first p-type GaN layer (411) on the substrate (10).
  9. 9. The transistor of claim 7, further comprising a passivation layer (60), the passivation layer (60) comprising portions between the grids filling the grid portions (53).
  10. 10. A transistor according to any of claims 1 to 6, characterized in that the first gate structure (4 a) and the second gate structure (4 b) are symmetrically arranged with respect to the centre line of the first electrode (31) and the second electrode (32).

Description

Bidirectional-conduction transistor and preparation method thereof Technical Field The disclosure relates to the field of power electronics, and in particular relates to a bidirectional-conduction transistor and a preparation method thereof. Background The transistor has the advantages of high electron mobility, high operating frequency, low noise and the like, and is widely applied to various electrical appliances. In the related art, a transistor includes a semiconductor multilayer body on a substrate, and a gate electrode, a source electrode, and a drain electrode on the semiconductor multilayer body. In unidirectional switching applications, where the source and drain roles are fixed, the gate drive circuit pulls the gate voltage above the on threshold or below the off threshold to control the current flowing from the fixed drain to the fixed source, such drive logic is unidirectional and fixed. However, in applications requiring bi-directional switching, two transistors in series must be provided and separately provided with independent and synchronized gate drive signals, which increases the complexity and cost of the drive circuit and makes the circuit layout more complex. Disclosure of Invention The embodiment of the disclosure provides a transistor with bidirectional conduction and a preparation method thereof, which can realize bidirectional conduction of the transistor and reduce the complexity of circuit layout. The technical scheme is as follows: On one hand, the embodiment of the disclosure provides a transistor, which comprises a substrate, a semiconductor multilayer body, a first electrode, a second electrode and a grid control structure, wherein the semiconductor multilayer body is positioned on the surface of the substrate, the grid control structure comprises a first grid control structure and a second grid control structure, the first electrode, the first grid control structure, the second grid control structure and the second electrode are sequentially arranged on the semiconductor multilayer body at intervals along the same direction, and the first grid control structure and the second grid control structure comprise a p-type layer and a grid electrode which are sequentially stacked on the semiconductor multilayer body. Optionally, the transistor further comprises a first semiconductor material layer, wherein the first semiconductor material layer is located between the semiconductor multilayer body and the grid control structure, and comprises a first strip-shaped part, a second strip-shaped part and a grid part connected with the first strip-shaped part and the second strip-shaped part. Optionally, the first stripe is located between the first gate structure and the semiconductor multilayer body, and the second stripe is located between the second gate structure and the semiconductor multilayer body. Optionally, the grid part includes a plurality of third strip-shaped parts and a plurality of fourth strip-shaped parts, the plurality of third strip-shaped parts are arranged on the semiconductor multilayer body at intervals along a first direction, the first direction is an arrangement direction of the first electrode, the first grid control structure, the second grid control structure and the second electrode, the plurality of fourth strip-shaped parts are arranged on the semiconductor multilayer body at intervals along a second direction, the second direction intersects with the first direction, and the third strip-shaped parts intersect with each of the fourth strip-shaped parts. Optionally, each of the fourth strip-shaped parts includes a first end and a second end, the first end is connected to the first strip-shaped part, and the second end is connected to the second strip-shaped part. Optionally, the first semiconductor material layer includes a u-type GaN layer. Optionally, the p-type layer includes a first p-type GaN layer and a second p-type GaN layer stacked in sequence, and the doping concentration of the first p-type GaN layer is lower than that of the second p-type GaN layer. Optionally, the orthographic projection of the second p-type GaN layer on the substrate is located within the orthographic projection of the first p-type GaN layer on the substrate. Optionally, the transistor further comprises a passivation layer comprising a portion between the grids filling the grid portion. Optionally, the first gate structure and the second gate structure are symmetrically arranged about a center line of the first electrode and the second electrode. The technical scheme provided by the embodiment of the disclosure has the beneficial effects that at least: The transistor provided by the embodiment of the disclosure uses two independent grid control structures on the semiconductor multilayer body to switch the current path, so that the transistor can automatically adjust the roles of source and drain according to the voltage polarity, and no additional serial devices or synchronous