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CN-122002842-A - High electron mobility transistor and preparation method thereof

CN122002842ACN 122002842 ACN122002842 ACN 122002842ACN-122002842-A

Abstract

The disclosure provides a high electron mobility transistor and a preparation method thereof, and belongs to the technical field of semiconductors. The high electron mobility transistor comprises an epitaxial layer, a gate electrode and a connecting metal, wherein the gate electrode is positioned on one side of the epitaxial layer and comprises a gate bus and a plurality of gate structures, the gate bus surrounds the outside of the gate structures, the gate structures are respectively connected with the gate bus, the connecting metal is positioned on one side of the gate electrode, which is away from the epitaxial layer, the connecting metal comprises a connecting bus and a gate connecting structure, the surrounding track of the connecting bus is consistent with the surrounding track of the gate bus, the connecting bus is connected with the gate bus, the gate connecting structure is positioned in the surrounding area of the connecting bus, and the gate connecting structure is connected with the connecting bus. The present disclosure is capable of having both physical shielding and electrical shielding effects.

Inventors

  • WANG RUI
  • Chen Kuangli
  • YANG YING
  • YANG TING
  • Jiang Aoxuan
  • ZHANG ZHONGYU

Assignees

  • 京东方华灿光电(广东)有限公司

Dates

Publication Date
20260508
Application Date
20251222

Claims (10)

  1. 1. A high electron mobility transistor, characterized by comprising an epitaxial layer (10), a gate electrode (20) and a connection metal (30); The gate electrode (20) is positioned on one side of the epitaxial layer (10), the gate electrode (20) comprises a gate bus bar (210) and a plurality of gate structures (220), the gate bus bar (210) surrounds the plurality of gate structures (220), and the plurality of gate structures (220) are respectively connected with the gate bus bar (210); The connection metal (30) is located on one side, facing away from the epitaxial layer (10), of the gate electrode (20), the connection metal (30) comprises a connection bus (310) and a gate connection structure (320), the surrounding track of the connection bus (310) is consistent with that of the gate bus (210), the connection bus (310) is connected with the gate bus (210), the gate connection structure (320) is located in the surrounding area of the connection bus (310), and the gate connection structure (320) is connected with the connection bus (310).
  2. 2. The hemt of claim 1, wherein two adjacent gate structures (220) are connected and enclose a ring-shaped structure; The gate electrode (20) further comprises a gate connecting line (230), and the two gate structures (220) surrounding the annular structure are connected with the gate bus (210) together through the gate connecting line (230).
  3. 3. The high electron mobility transistor of claim 1, comprising a first dielectric layer (40) and a second dielectric layer (50); The first dielectric layer (40) and the second dielectric layer (50) are sequentially stacked on one side of the epitaxial layer (10), the first dielectric layer (40) is filled and covers the gate electrode (20), and the second dielectric layer (50) is filled and covers the connecting bus (310).
  4. 4. A hemt according to claim 3, characterized in that the connection bus (310) extends through the second dielectric layer (50) and the first dielectric layer (40) and is connected to the gate bus (210); The grid connection structure (320) penetrates through one side, opposite to the first dielectric layer (40), of the second dielectric layer (50) and is exposed outside.
  5. 5. The high electron mobility transistor of claim 3, comprising an ohmic bus bar (60); the ohmic bus bar (60) is positioned on one side of the gate bus bar (210) facing the epitaxial layer (10), and the surrounding track of the ohmic bus bar (60) is consistent with the surrounding track of the gate bus bar (210).
  6. 6. The hemt of claim 5, wherein the epitaxial layer (10) comprises an isolation structure (110); the isolation structure (110) is positioned at a position of the epitaxial layer (10) close to the first dielectric layer (40); A portion of the ohmic bus bar (60) is located within the isolation structure (110), and another portion of the ohmic bus bar (60) is located within the first dielectric layer (40).
  7. 7. The high electron mobility transistor of claim 2, comprising a plurality of ohmic electrodes (70); a plurality of ohmic electrodes (70) are positioned on one side of the epitaxial layer (10), and one ohmic electrode (70) is positioned in an annular structure surrounded by two adjacent gate structures (220).
  8. 8. The hemt of claim 7, wherein said connection metal (30) further comprises an ohmic connection structure (330) and a source connection structure (340); the ohmic connection structures (330) are in one-to-one correspondence with the ohmic electrodes (70) of the first portion; The source connection structure (340) is connected to the ohmic electrode (70) of the first portion through the ohmic connection structure (330).
  9. 9. The hemt of claim 7, wherein said connection metal (30) further comprises an ohmic connection structure (330) and a drain connection structure (350); the ohmic connection structures (330) are in one-to-one correspondence with the ohmic electrodes (70) of the second portion; The drain connection structure (350) is connected to the ohmic electrode (70) of the second portion through the ohmic connection structure (330).
  10. 10. A method of fabricating a high electron mobility transistor, comprising: growing an epitaxial layer (10); depositing a gate metal layer on one side of the epitaxial layer (10), and photoetching to form a gate bus (210) and a plurality of gate structures (220), wherein the gate bus (210) surrounds the plurality of gate structures (220), and the plurality of gate structures (220) are respectively connected with the gate bus (210); And depositing a connecting metal layer on one side of the gate metal layer, and photoetching to form a connecting bus bar (310) and a gate connecting structure (320), wherein the surrounding track of the connecting bus bar (310) is consistent with the surrounding track of the gate bus bar (210), the connecting bus bar (310) is connected with the gate bus bar (210), the gate connecting structure (320) is positioned in the surrounding area of the connecting bus bar (310), and the gate connecting structure (320) is connected with the connecting bus bar (310).

Description

High electron mobility transistor and preparation method thereof Technical Field The disclosure belongs to the technical field of semiconductors, and particularly relates to a high electron mobility transistor and a preparation method thereof. Background A high electron mobility transistor (High electron mobility transistor, HEMT) is a field effect transistor, mainly comprising both depletion and enhancement types. In the related art, the depletion type high electron mobility transistor has the characteristics of smaller on-resistance and higher gate reliability, and is widely applied. However, since the threshold voltage of the depletion type high electron mobility transistor is negative, it is required to use the depletion type high electron mobility transistor in combination with a low voltage MOS device, i.e., a Cascode (Cascode) structure. In the process of sealing, a packaging metal ring is required to be designed in the device so as to isolate water and oxygen in the environment, thereby ensuring the packaging reliability. However, the packaging metal ring in the related art is usually designed in a floating manner, and only plays a role of physical shielding, but cannot realize electrical shielding. Disclosure of Invention The embodiment of the disclosure provides a high electron mobility transistor and a preparation method thereof, which can have the effects of physical shielding and electric shielding. The technical scheme is as follows: In one aspect, embodiments of the present disclosure provide a high electron mobility transistor including an epitaxial layer, a gate electrode, and a connection metal; The gate electrode is positioned on one side of the epitaxial layer and comprises a gate bus and a plurality of gate structures, the gate bus surrounds the plurality of gate structures, and the plurality of gate structures are respectively connected with the gate bus; The connection metal is located on one side of the gate electrode, which is opposite to the epitaxial layer, the connection metal comprises a connection bus and a gate connection structure, the surrounding track of the connection bus is consistent with that of the gate bus, the connection bus is connected with the gate bus, the gate connection structure is located in the surrounding area of the connection bus, and the gate connection structure is connected with the connection bus. In one implementation of the disclosure, two adjacent gate structures are connected and form an annular structure; The gate electrode further comprises a gate connecting wire, and the two gate structures surrounding the annular structure are connected with the gate bus through the gate connecting wire. In one implementation of the present disclosure, a first dielectric layer and a second dielectric layer; The first dielectric layer and the second dielectric layer are sequentially stacked on one side of the epitaxial layer, the first dielectric layer is filled and covers the gate electrode, and the second dielectric layer is filled and covers the connecting bus. In one implementation of the disclosure, the connection bus penetrates through the second dielectric layer and the first dielectric layer and is connected with the gate bus; the grid connection structure penetrates through one side, opposite to the first dielectric layer, of the second dielectric layer and is exposed outside. In one implementation of the present disclosure, an ohmic bus bar; The ohmic bus bar is positioned on one side of the grid bus bar facing the epitaxial layer, and the surrounding track of the ohmic bus bar is consistent with the surrounding track of the grid bus bar. In one implementation of the present disclosure, the epitaxial layer includes an isolation structure; the isolation structure is positioned at the position of the epitaxial layer close to the first dielectric layer; A portion of the ohmic bus bar is located within the isolation structure and another portion of the ohmic bus bar is located within the first dielectric layer. In one implementation of the present disclosure, a plurality of ohmic electrodes are included; and a plurality of ohmic electrodes are positioned on one side of the epitaxial layer, and one ohmic electrode is positioned in an annular structure surrounded by two adjacent grid structures. In one implementation of the present disclosure, the connection metal further includes an ohmic connection structure and a source connection structure; the ohmic connection structures are in one-to-one correspondence with the ohmic electrodes of the first part; the source connection structure is connected with the ohmic electrode of the first portion through the ohmic connection structure. In one implementation of the present disclosure, the connection metal further includes an ohmic connection structure and a drain connection structure; The ohmic connection structures are in one-to-one correspondence with the ohmic electrodes of the second part; the drain electrode