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CN-122002843-A - Transistor and manufacturing method thereof

CN122002843ACN 122002843 ACN122002843 ACN 122002843ACN-122002843-A

Abstract

The disclosure provides a transistor and a manufacturing method thereof, and belongs to the technical field of semiconductors. The transistor comprises a heterojunction, a plurality of electrodes and a connecting structure, wherein the electrodes are electrically connected with the heterojunction and are arranged at intervals in parallel along a first direction, the electrodes comprise a plurality of grids, a plurality of sources and a plurality of drains, the electrodes positioned on two sides of the electrodes are the sources, one grid, one drain and one grid are sequentially arranged between any two adjacent sources, one ends of the two adjacent drains are connected through a first connecting structure, and/or one ends of the two adjacent grids are connected through a second connecting structure, the first connecting structure and the connected drains are positioned on the same layer, and the second connecting structure and the connected grids are positioned on the same layer. The current uniformity can be improved, and the performance of the transistor can be improved.

Inventors

  • YANG TING
  • WANG RUI
  • YANG YING
  • WANG JIANGBO

Assignees

  • 京东方华灿光电(浙江)有限公司

Dates

Publication Date
20260508
Application Date
20251222

Claims (10)

  1. 1. The transistor is characterized by comprising a heterojunction, a plurality of electrodes and a connecting structure, wherein the electrodes are electrically connected with the heterojunction and are arranged at intervals in parallel along a first direction, and the surface of each electrode far away from the heterojunction is in a strip shape and the length direction of each electrode is intersected with the first direction; The electrodes comprise a plurality of grids (3), a plurality of sources (4) and a plurality of drains (5), the two sides of the plurality of electrodes are provided with the sources (4), and one grid (3), one drain (5) and one grid (3) are sequentially arranged between any two adjacent sources (4); one end of each two adjacent drain electrodes (5) is connected through a first connecting structure (501); and/or; One end of each two adjacent grid electrodes (3) is connected through a second connecting structure (301), the first connecting structure (501) and the connected drain electrode (5) are located on the same layer, and the second connecting structure (301) and the connected grid electrodes (3) are located on the same layer.
  2. 2. The transistor according to claim 1, wherein the first connection structures (501) are respectively connected to the same ends of two adjacent drain electrodes (5), and the first connection structures (501) are located at the same ends of the plurality of drain electrodes (5), and the first connection structures (501) are arc-shaped structures.
  3. 3. The transistor according to claim 2, characterized in that the intrados of the first connection structure (501) is an arc of a circle and has a radius of 20 μm-30 μm.
  4. 4. The transistor according to claim 2, wherein a width of a surface of the first connection structure (501) away from the heterojunction is the same as a width of a surface of the drain electrode (5) away from the heterojunction, a width direction of the first connection structure (501) is perpendicular to an extending direction of the first connection structure (501), and a width direction of the drain electrode (5) is perpendicular to a length direction of the drain electrode (5).
  5. 5. The transistor according to claim 4, characterized in that the width of the first connection structure (501) is 1 μm-3 μm.
  6. 6. A transistor according to claim 2, characterized in that one end of two gates (3) located between two adjacent drains (5) is connected by one of the second connection structures (301), and the other ends of two adjacent gates (3) located on both sides of the same drain (5) are connected by one of the second connection structures (301).
  7. 7. The transistor according to claim 6, wherein the second connection structure (301) is an arc-shaped structure.
  8. 8. The transistor according to claim 7, characterized in that the intrados of the second connection structure (301) is an arc of a circle and has a radius of 15 μm-25 μm.
  9. 9. A transistor according to any of claims 1-8, characterized in that the transistor further comprises a metal interconnect structure (7), the metal interconnect structure (7) being located on a side of the plurality of electrodes remote from the heterojunction, the metal interconnect structure (7) comprising a first metal bus (71) connected to the plurality of gates (3), a second metal bus (72) connected to the plurality of sources (4) and a third metal bus (73) connected to the plurality of drains (5).
  10. 10. A method of fabricating a transistor, the method comprising: Forming a heterojunction; Manufacturing a plurality of electrodes, wherein the surface of each electrode far away from the heterojunction is in a strip shape, and the length direction of each electrode is intersected with the first direction; The electrodes are arranged on two sides of the electrodes, and one grid electrode, one drain electrode and one grid electrode are sequentially arranged between any two adjacent source electrodes; one end of each two adjacent drain electrodes is connected through a first connecting structure; and/or one end of each two adjacent grid electrodes is connected through a second connecting structure, the first connecting structure and the connected drain electrode are positioned on the same layer, and the second connecting structure and the connected grid electrodes are positioned on the same layer.

Description

Transistor and manufacturing method thereof Technical Field The disclosure belongs to the technical field of semiconductors, and particularly relates to a transistor and a manufacturing method thereof. Background In a transistor, spontaneous polarization and piezoelectric polarization effects are induced at the heterojunction interface, thereby inducing a high-concentration and high-mobility two-dimensional electron gas. In the related art, a transistor includes a heterojunction, a plurality of electrodes, and a plurality of metal buses. The plurality of electrodes are electrically connected to the heterojunction. The plurality of electrodes includes a plurality of gates, a plurality of sources, and a plurality of drains. The drain, gate and source are all elongated finger structures and alternate in parallel along the same direction, such as source-gate-drain-gate-source, etc. In order to realize effective connection of an external circuit, each finger electrode is connected with a corresponding metal bus positioned on an upper layer, and the finger electrodes of the same type are connected with the same metal bus. However, due to the slight asymmetry in the connection locations of the finger electrodes to the upper metal bus lines and the resistance of the upper metal bus lines themselves, uneven or even overload current is caused to occur to the finger electrodes. And when the finger electrode is overloaded with current, the temperature of the finger electrode is increased sharply. This causes a further increase in the intrinsic resistance of the overheated electrode, since both the carrier mobility of the semiconductor material and the conductivity of the metal conductor decrease with increasing temperature. Eventually, the equivalent resistance of the electrodes after parallel connection increases, which is manifested as an increase in the on-resistance of the transistor (the equivalent total resistance between the drain and the source after the transistor is turned on), so that the maximum output current capability of the transistor decreases. Disclosure of Invention The embodiment of the disclosure provides a transistor and a manufacturing method thereof, which can improve current uniformity and improve the performance of the transistor. The technical scheme is as follows: The embodiment of the disclosure provides a transistor, which comprises a heterojunction, a plurality of electrodes and a connecting structure, wherein the electrodes are electrically connected with the heterojunction and are arranged at intervals in parallel along a first direction, the surface of each electrode far away from the heterojunction is in a strip shape, the length direction of each electrode is intersected with the first direction, the electrodes on two sides of the electrodes are the sources, one grid, one drain and one grid are sequentially arranged between any two adjacent sources, one ends of the two adjacent drains are connected through a first connecting structure, and/or one ends of the two adjacent grids are connected through a second connecting structure, the first connecting structure and the connected drains are located on the same layer, and the second connecting structure and the connected grids are located on the same layer. In one implementation of the disclosure, the first connection structures are respectively connected to the same ends of two adjacent drain electrodes, and the first connection structures are located at the same ends of the drain electrodes, and the first connection structures are arc structures. In one implementation of the disclosure, the intrados surface of the first connection structure is an arc surface and has a radius of 20 μm-30 μm. In one implementation of the disclosure, a width of a surface of the first connection structure away from the heterojunction is the same as a width of a surface of the drain away from the heterojunction, a width direction of the first connection structure is perpendicular to an extension direction of the first connection structure, and a width direction of the drain is perpendicular to a length direction of the drain. In one implementation of the present disclosure, the first connection structure has a width of 1 μm to 3 μm. In one implementation of the disclosure, one ends of two gates between two adjacent drains are connected by one second connection structure, and the other ends of two adjacent gates on two sides of the same drain are connected by one second connection structure. In one implementation of the present disclosure, the second connection structure is an arc structure. In one implementation of the present disclosure, the intrados surface of the second connection structure is an arc surface and has a radius of 15 μm to 25 μm. In one implementation of the disclosure, the transistor further includes a metal interconnect structure located on a side of the plurality of electrodes remote from the heterojunction, the metal interconnect struct