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CN-122002844-A - Enhanced transistor and manufacturing method thereof

CN122002844ACN 122002844 ACN122002844 ACN 122002844ACN-122002844-A

Abstract

The disclosure provides an enhanced transistor and a manufacturing method thereof, and belongs to the technical field of semiconductors. The enhancement transistor comprises a channel layer, a barrier layer, a gate dielectric layer and a plurality of gates, wherein the channel layer, the barrier layer and the gate dielectric layer are sequentially laminated, the gates are positioned on one side of the gate dielectric layer away from the channel layer and are arranged at intervals along a first direction, and the gate distance between two adjacent gates is smaller than 200nm. The present disclosure may improve the performance of the device.

Inventors

  • Jiang Aoxuan
  • WANG RUI
  • Chen Kuangli
  • WANG JIANGBO

Assignees

  • 京东方华灿光电(浙江)有限公司

Dates

Publication Date
20260508
Application Date
20251223

Claims (10)

  1. 1. An enhancement mode transistor, characterized in that the enhancement mode transistor comprises a channel layer (1), a barrier layer (2), a gate dielectric layer (3) and a plurality of gates (4); The channel layer (1), the barrier layer (2) and the gate dielectric layer (3) are sequentially laminated; The grid electrodes (4) are arranged on one side, far away from the channel layer (1), of the grid dielectric layer (3) at intervals along the first direction, and the grid electrode spacing between two adjacent grid electrodes (4) is smaller than 200nm.
  2. 2. The enhancement mode transistor according to claim 1, further comprising a first dielectric layer (5) stacked on the barrier layer (2), the first dielectric layer (5) having therein first recesses (101) in one-to-one correspondence with the plurality of gates (4); a plurality of second grooves (102) are formed in the barrier layer (2) and the channel layer (1) below the first grooves (101), and the second grooves (102) are in one-to-one correspondence with the first grooves (101) and are communicated with each other to form gate grooves; Along the first direction, the distance between two adjacent first grooves (101) is smaller than 200nm.
  3. 3. The enhancement transistor according to claim 2, wherein the opening size of the first recess (101) is larger than the opening size of the second recess (102), the opening sizes of the first recess (101) and the second recess (102) being the length of the opening along the first direction.
  4. 4. An enhancement transistor according to claim 3, characterized in that the opening size of the first recess (101) is larger than 500nm and smaller than 600nm, and the opening size of the second recess (102) is not smaller than 400nm.
  5. 5. The enhancement-mode transistor according to claim 2, wherein the first dielectric layer (5) is a SiO 2 layer, an Al 2 O 3 layer, a SiN layer or a Si x N y layer.
  6. 6. The enhancement-mode transistor according to claim 2, further comprising a first passivation layer (6) and a stop layer (7) stacked in sequence on the barrier layer (2), the stop layer (7) being located on a side of the first dielectric layer (5) facing the barrier layer (2); The first groove (101) penetrates through the first passivation layer (6) and the stop layer (7), and the side wall of the first groove (101) at the interface between the first passivation layer (6) and the stop layer (7) is provided with a third step (603) and a fourth step (604), and the third step (603) and the fourth step (604) are respectively positioned on two sides of the first groove (101) along the direction perpendicular to the first direction.
  7. 7. The enhancement transistor according to claim 6, wherein the first passivation layer (6) is a SiN layer and the stop layer (7) is an AlN layer.
  8. 8. A method of fabricating an enhancement mode transistor, the method comprising: Sequentially forming a laminated channel layer, a barrier layer and a gate dielectric layer; and forming a plurality of grid electrodes on the grid dielectric layer, wherein the grid electrodes are arranged at intervals along a first direction, and the grid electrode spacing between two adjacent grid electrodes is smaller than 200nm.
  9. 9. The method of manufacturing of claim 8, wherein sequentially forming the channel layer, the barrier layer, and the gate dielectric layer stacked together comprises: forming the channel layer, the barrier layer and the first dielectric layer which are sequentially stacked on a substrate; wet etching is carried out on the first dielectric layer, so that a pre-groove for defining a first groove is formed in the first dielectric layer; Etching the first dielectric layer, the channel layer and the barrier layer to enable the pre-groove to be changed into a first groove, forming a plurality of second grooves in the barrier layer and the channel layer below the first groove, wherein the second grooves are in one-to-one correspondence and communicated with the first groove to form a grid groove, and the first grooves extend from the upper surface of the first dielectric layer to the surface of the barrier layer facing the first dielectric layer; the opening size of the first groove is larger than that of the second groove, the opening sizes of the first groove and the second groove are the lengths of the openings along the first direction, and the distance between two adjacent first grooves is smaller than 200nm; and forming the gate dielectric layer, wherein the gate dielectric layer covers the bottom and the side wall of the gate groove and the upper surface of the first dielectric layer.
  10. 10. The method of claim 9, wherein wet etching the first dielectric layer, the channel layer, and the barrier layer comprises: Forming a metal mask layer on the first dielectric layer, wherein the metal mask layer fills the pre-groove and covers the upper surface of the first dielectric layer; Forming a dielectric mask layer on the metal mask layer, wherein the dielectric mask layer is provided with dielectric grooves aligned with the plurality of pre-grooves one by one; Wet etching the metal mask layer by taking the dielectric mask layer as a mask to form a plurality of metal grooves which are communicated with the pre-grooves and the dielectric grooves which are mutually corresponding, wherein the opening size of the metal grooves along the first direction is larger than that of the pre-grooves; And removing the dielectric mask layer, and etching the first dielectric layer, the channel layer and the barrier layer by taking the metal mask layer as a mask, so that the pre-grooves become the first grooves, and forming corresponding second grooves in the barrier layer and the channel layer right below each first groove.

Description

Enhanced transistor and manufacturing method thereof Technical Field The disclosure belongs to the technical field of semiconductors, and in particular relates to an enhanced transistor and a manufacturing method thereof. Background Transistors, particularly gallium nitride high electron mobility transistors, have demonstrated great potential for use in high frequency, high power electronics because of their excellent wide bandgap characteristics. In the related art, in order to improve device performance (e.g., pinch-off efficiency), very narrow and fully depleted channels are typically built into transistors. That is, a typical structure of a transistor includes a channel layer, a barrier layer stacked on the channel layer, a gate dielectric layer stacked on the barrier layer, and a plurality of gates on the gate dielectric layer. Each grid electrode applies an electric field to the channel layer through the grid dielectric layer so as to deplete two-dimensional electron gas below to form a depletion region. However, the spacing between adjacent gates is typically greater than 200nm, subject to the limitations of current photolithographic process accuracy. The size limitation causes that depletion regions generated by adjacent gates are difficult to fully overlap, so that two-dimensional electron gas in the region between the two gates cannot be completely pinched off, thereby affecting effective regulation and control of carriers in a channel layer and restricting further improvement of device performance. Disclosure of Invention The embodiment of the disclosure provides an enhanced transistor and a manufacturing method thereof, which can improve the performance of a device. The technical scheme is as follows: The embodiment of the disclosure provides an enhanced transistor, which comprises a channel layer, a barrier layer, a gate dielectric layer and a plurality of gates, wherein the channel layer, the barrier layer and the gate dielectric layer are sequentially laminated, the gates are positioned on one side of the gate dielectric layer away from the channel layer and are arranged at intervals along a first direction, and the gate distance between two adjacent gates is smaller than 200nm. In still another implementation manner of the present disclosure, the enhancement transistor further includes a first dielectric layer stacked on the barrier layer, wherein the first dielectric layer has first grooves corresponding to the gates one by one, the barrier layer below the first grooves and the channel layer have second grooves corresponding to the first grooves one by one and communicated with each other to form gate grooves, and a distance between two adjacent first grooves is smaller than 200nm along the first direction. In yet another implementation of the present disclosure, the first groove opening size is greater than the second groove opening size, the first groove and the second groove opening sizes are both lengths of the opening along the first direction. In yet another implementation of the present disclosure, the opening size of the first groove is greater than 500nm and less than 600nm, and the opening size of the second groove is not less than 400nm. In yet another implementation of the present disclosure, the first dielectric layer is a SiO 2 layer, an Al 2O3 layer, a SiN layer, or a Si xNy layer. In yet another implementation of the present disclosure, the enhancement transistor further includes a first passivation layer and a stop layer sequentially stacked on the barrier layer, the stop layer being located at a side of the first dielectric layer toward the barrier layer, the first groove penetrating through the first passivation layer and the stop layer, and a sidewall of the first groove at an interface between the first passivation layer and the stop layer having a third step and a fourth step, the third step and the fourth step being located at both sides of the first groove along a direction perpendicular to the first direction, respectively. In yet another implementation of the present disclosure, the first passivation layer is a SiN layer and the stop layer is an AlN layer. On the other hand, the invention further provides a manufacturing method of the enhanced transistor, which comprises the steps of sequentially forming a stacked channel layer, a barrier layer and a gate dielectric layer, and forming a plurality of gates on the gate dielectric layer, wherein the gates are arranged at intervals along a first direction, and the gate interval between two adjacent gates is smaller than 200nm. In a further implementation manner of the present disclosure, the sequentially forming the channel layer, the barrier layer and the gate dielectric layer stacked together includes forming the channel layer, the barrier layer and the first dielectric layer stacked together on a substrate, performing wet etching on the first dielectric layer to form a pre-groove for defining a first groove in the f