CN-122002845-A - High electron mobility transistor and preparation method thereof

CN122002845ACN 122002845 ACN122002845 ACN 122002845ACN-122002845-A

Abstract

The disclosure provides a high electron mobility transistor and a preparation method thereof, and belongs to the technical field of semiconductors. The high electron mobility transistor comprises an epitaxial layer, a gate structure, a source electrode structure and a drain electrode structure, wherein the epitaxial layer comprises a first channel layer, a first barrier layer, a second channel layer, a second barrier layer and a communicating depletion layer, a groove is formed in one side of the second channel layer and one side of the second barrier layer, the communicating depletion layer is located in the groove and extends to the first barrier layer along the side walls of the second barrier layer and the second channel layer, orthographic projection of the gate structure in the epitaxial growth direction covers the communicating depletion layer and at least part of the first barrier layer and the second barrier layer, the source electrode structure is located in the groove, penetrates through the first barrier layer and is connected with the first channel layer, and the drain electrode structure penetrates through the second barrier layer, the second channel layer and the first barrier layer and is connected with the first channel layer. The method can realize the utilization of the dimension in the vertical direction with lower preparation difficulty.

Inventors

WANG RUI
YANG YING
Chen Kuangli
ZHANG ZHONGYU
JIANG ZHULIN
Jiang Aoxuan
YANG TING

Assignees

京东方华灿光电(广东)有限公司

Dates

Publication Date: 20260508
Application Date: 20251223

Claims (10)

1. A high electron mobility transistor comprising an epitaxial layer (10), a gate structure (20), a source structure (30) and a drain structure (40); The epitaxial layer (10) comprises a first channel layer (110), a first barrier layer (120), a second channel layer (130), a second barrier layer (140) and a communication depletion layer (150), wherein the first channel layer (110), the first barrier layer (120), the second channel layer (130) and the second barrier layer (140) are sequentially stacked, one side of the second channel layer (130) and one side of the second barrier layer (140) are provided with grooves, the grooves extend from the second barrier layer (140) to the first barrier layer (120), the communication depletion layer (150) is positioned in the grooves, and the grooves extend to the first barrier layer (120) along the side walls of the second barrier layer (140) and the second channel layer (130); an orthographic projection of the gate structure (20) in an epitaxial growth direction covers the connected depletion layer (150), and at least part of the first barrier layer (120) and the second barrier layer (140); The source structure (30) is located in the trench, and the source structure (30) penetrates through the first barrier layer (120) and is connected with the first channel layer (110); The drain structure (40) penetrates the second barrier layer (140), the second channel layer (130), the first barrier layer (120) and is connected with the first channel layer (110).
2. The hemt of claim 1, wherein said connected depletion layer (150) is an N-type GaN layer; and in the direction parallel to the epitaxial growth direction, the thickness of the connected depletion layer (150) is 10-25 nm.
3. The hemt of claim 1, wherein the first channel layer (110) is an unintentionally doped GaN layer, the first channel layer (110) having a thickness of 50-200 nm; The first barrier layer (120) is an Al x Ga 1-x N layer, the thickness of the first barrier layer (120) is 8-30 nm, and x is more than or equal to 0.1 and less than or equal to 0.4.
4. The hemt of claim 1, wherein the second channel layer (130) is an unintentionally doped GaN layer, the second channel layer (130) having a thickness of 50-200 nm; The first barrier layer (120) is an Al x Ga 1-x N layer, the thickness of the first barrier layer (120) is 8-30 nm, and x is more than or equal to 0.1 and less than or equal to 0.4.
5. The hemt of claim 1, wherein said source structure (30) comprises an ohmic source (310) and a source electrode (320); -a first end of the ohmic source (310) is located within the first channel layer (110), and a second end of the ohmic source (310) is located outside the first barrier layer (120); the source electrode (320) is electrically connected to the second end of the ohmic source electrode (310).
6. The hemt of claim 5, wherein said source structure (30) further comprises a source protection structure (330); The source protection structure (330) is located between the ohmic source electrode (310) and the source electrode (320), and the source protection structure (330) is made of the same material as the gate structure (20).
7. The high electron mobility transistor of claim 1, wherein the drain structure (40) comprises an ohmic drain (410) and a drain electrode (420); -a first end of the ohmic drain (410) is located within the first channel layer (110), and a second end of the ohmic drain (410) is located outside the second barrier layer (140); the drain electrode (420) is electrically connected to the second end of the ohmic drain electrode (410).
8. The hemt of claim 7, wherein said drain structure (40) further comprises a drain protection structure (430); The drain protection structure (430) is located between the ohmic drain (410) and the drain electrode (420), and the drain protection structure (430) is made of the same material as the gate structure (20).
9. The high electron mobility transistor of claim 1, further comprising a gate dielectric layer (50); the gate dielectric layer (50) covers the first barrier layer (120), the communication depletion layer (150), the second barrier layer (140), and at least a portion of the gate dielectric layer (50) is located between the gate structure (20) and the communication depletion layer (150).
10. A method of fabricating a high electron mobility transistor, comprising: sequentially preparing a first channel layer (110), a first barrier layer (120), a second channel layer (130) and a second barrier layer (140); -lithographically forming the second barrier layer (140) and the second channel layer (130) to form a trench extending from the second barrier layer (140) to the first barrier layer (120); -preparing a communicating depletion layer (150) such that the communicating depletion layer (150) is located within the trench and extends along sidewalls of the second barrier layer (140) and the second channel layer (130) to the first barrier layer (120); The method comprises the steps of respectively preparing a gate structure (20), a source structure (30) and a drain structure (40), wherein orthographic projection of the gate structure (20) in the epitaxial growth direction covers the communicated depletion layer (150), and at least part of the first barrier layer (120) and the second barrier layer (140), the source structure (30) is located in the groove, the source structure (30) penetrates through the first barrier layer (120) and is connected with the first channel layer (110), and the drain structure (40) penetrates through the second barrier layer (140), the second channel layer (130), the first barrier layer (120) and is connected with the first channel layer (110).

Description

High electron mobility transistor and preparation method thereof Technical Field The disclosure belongs to the technical field of semiconductors, and particularly relates to a high electron mobility transistor and a preparation method thereof. Background A high electron mobility transistor (High electron mobility transistor, HEMT) is a field effect transistor, mainly comprising both depletion and enhancement types. In the related art, the depletion type high electron mobility transistor has the characteristics of smaller on-resistance and higher gate reliability, and is widely applied. Depletion-mode high electron mobility transistors are horizontally structured devices that cannot exhibit this dimension in the vertical direction. If the high electron mobility transistor is designed by a mode of forming a plurality of two-dimensional electron gases by a mode of stacking a plurality of channels, that is, growing a plurality of circulating channel layers and barrier layers, the depth of the obtained two-dimensional electron gases is deeper, and the turn-off cannot be completed through a horizontal gate structure. The requirements on the lithography precision of the vertical gate structure or the trench gate structure are high, and the critical dimension is often lower than 0.1 μm, so that the preparation difficulty is high. Disclosure of Invention The embodiment of the disclosure provides a high electron mobility transistor and a preparation method thereof, which can realize the utilization of the dimension in the vertical direction with lower preparation difficulty. The technical scheme is as follows: in one aspect, embodiments of the present disclosure provide a high electron mobility transistor including an epitaxial layer, a gate structure, a source structure, and a drain structure; The epitaxial layer comprises a first channel layer, a first barrier layer, a second channel layer, a second barrier layer and a communication depletion layer, wherein the first channel layer, the first barrier layer, the second channel layer and the second barrier layer are sequentially stacked, a groove is formed in one side of each of the second channel layer and the second barrier layer, the groove extends from the second barrier layer to the first barrier layer, and the communication depletion layer is positioned in the groove and extends to the first barrier layer along the side walls of the second barrier layer and the second channel layer; orthographic projection of the grid structure in the epitaxial growth direction covers the communicated depletion layer and at least part of the first barrier layer and the second barrier layer; The source electrode structure is positioned in the groove, penetrates through the first barrier layer and is connected with the first channel layer; The drain structure penetrates through the second barrier layer, the second channel layer, the first barrier layer and is connected with the first channel layer. In one implementation of the present disclosure, the connected depletion layer is an N-type GaN layer; and in the direction parallel to the epitaxial growth direction, the thickness of the connected depletion layer is 10-25 nm. In one implementation of the disclosure, the first channel layer is an unintentionally doped GaN layer, and the thickness of the first channel layer is 50-200 nm; The first barrier layer is an Al xGa1-x N layer, the thickness of the first barrier layer is 8-30 nm, and x is more than or equal to 0.1 and less than or equal to 0.4. In one implementation of the disclosure, the second channel layer is an unintentionally doped GaN layer, and the thickness of the second channel layer is 50-200 nm; The first barrier layer is an Al xGa1-x N layer, the thickness of the first barrier layer is 8-30 nm, and x is more than or equal to 0.1 and less than or equal to 0.4. In one implementation of the present disclosure, the source structure includes an ohmic source and a source electrode; The first end of the ohmic source electrode is positioned in the first channel layer, and the second end of the ohmic source electrode is positioned outside the first barrier layer; the source electrode is electrically connected with the second end of the ohmic source electrode. In one implementation of the present disclosure, the source structure further includes a source protection structure; the source electrode protection structure is positioned between the ohmic source electrode and the source electrode, and the material of the source electrode protection structure is consistent with that of the grid electrode structure. In one implementation of the present disclosure, the drain structure includes an ohmic drain and a drain electrode; The first end of the ohmic drain electrode is positioned in the first channel layer, and the second end of the ohmic drain electrode is positioned outside the second barrier layer; the drain electrode is electrically connected with the second end of the ohmic