CN-122002846-A - High electron mobility transistor device and method of manufacturing the same

Abstract

A high electron mobility transistor device and a method of fabricating the same, wherein the high electron mobility transistor device includes a channel layer, a barrier layer, a gate structure, a dielectric layer, a drain, a first source field plate, and a second source field plate. The barrier layer is disposed on the channel layer. The gate structure is disposed on the barrier layer. The dielectric layer is disposed on the barrier layer. The drain electrode is etched by the source/drain metal layer. The first source electrode field plate is arranged on the dielectric layer and positioned between the grid structure and the drain electrode, wherein the first source electrode field plate is formed by etching the source/drain electrode metal layer. The second source field plate is arranged on the dielectric layer and part of the second source field plate covers part of the first source field plate.

Inventors

• HE WEIZHI

Assignees

• 英属开曼群岛商海珀电子股份有限公司

Dates

Publication Date

20260508

Application Date

20260212

Claims (8)

1. 1. A high electron mobility transistor device, comprising: a channel layer; a barrier layer disposed on the channel layer; A gate structure disposed on the barrier layer; a dielectric layer disposed on the barrier layer; A drain electrode etched by a source/drain metal layer; a first source field plate disposed between the gate structure and the drain electrode and etched from the source/drain metal layer, and And a second source field plate arranged on the dielectric layer and part of the second source field plate covers part of the first source field plate.
2. 2. The hemt device of claim 1, wherein said dielectric layer covered by said second source field plate has a first thickness and said dielectric layer covered by said first source field plate has a second thickness, wherein said first thickness is less than said second thickness.
3. 3. The hemt device of claim 1, wherein a portion of said second source field plate is located between said gate structure and said first source field plate.
4. 4. The hemt device of claim 1, wherein said second source field plate is a titanium nitride layer and said dielectric layer is a silicon nitride layer.
5. 5. A method of fabricating a high electron mobility transistor device, comprising the steps of: forming a barrier layer on a channel layer; forming a dielectric layer on the barrier layer; Defining and etching the dielectric layer by using a first photomask to form a drain electrode recess; Forming a source/drain metal layer on the dielectric layer, wherein the source/drain metal layer fills the drain recess; defining and etching the source/drain metal layer by using a second photomask to form a drain and a first source field plate, wherein the first source field plate is positioned between the drain and the gate structure; Forming a second source field plate metal layer on the dielectric layer, the drain electrode and the first source field plate, and A third mask is used to define and etch the second source field plate metal layer to form a second source field plate, wherein a part of the second source field plate covers a part of the first source field plate.
6. 6. The method of claim 5, wherein the second mask defines a distance between the drain and the first source field plate and a distance between the drain and the second source field plate.
7. 7. The method of claim 5, wherein the dielectric layer covered by the second source field plate has a first thickness and the dielectric layer covered by the first source field plate has a second thickness, wherein the first thickness is less than the second thickness.
8. 8. The method of claim 5, wherein the second source field plate is located between the gate structure and the first source field plate.

Description

High electron mobility transistor device and method of manufacturing the same Technical Field The present invention relates to a high electron mobility transistor device and a method of fabricating the same, and more particularly, to a high electron mobility transistor device having a first source field plate formed with a source/drain Metal (SD Metal) layer and a method of fabricating the same. Background As the size of gallium nitride (GaN) power devices continues to shrink in order to pursue lower on-resistance (Rsp), multi-layer Source field plates (Source FIELD PLATE, SFP) and Source/drain electrodes have been the mainstream structures in limited gate-to-drain spacing (Lgd). However, when the prior art defines the second-order source field plate structure, two exposures are required by using different masks. The method has the technical bottlenecks that firstly, the resolution limit of exposure equipment is limited, the miniaturization design requirement of Lgd is difficult to correspondingly shorten, and secondly, repeated exposure not only increases the process cost, but also the risk of interlayer alignment offset (MISALIGNMENT) directly influences the product yield. Therefore, there is a need for improvement in how to simplify the process and to improve the alignment accuracy. Disclosure of Invention The present invention provides a high electron mobility transistor device and a method for manufacturing the same, which can reduce the number of masks used, thereby reducing the production cost. Another objective of the present invention is to provide a high electron mobility transistor device and a method for manufacturing the same, which can improve the interlayer alignment offset to greatly improve the product yield. It is still another object of the present invention to provide a high electron mobility transistor device and a method for fabricating the same to reduce on-resistance. To achieve the above objective, the hemt device of the present invention comprises a channel layer, a barrier layer, a gate structure, a dielectric layer, a drain electrode, a first source field plate, and a second source field plate. The barrier layer is disposed on the channel layer. The gate structure is disposed on the barrier layer. The dielectric layer is disposed on the barrier layer. The drain electrode is etched by the source/drain metal layer. The first source electrode field plate is arranged on the dielectric layer and positioned between the grid structure and the drain electrode, wherein the first source electrode field plate is formed by etching the source/drain electrode metal layer. The second source field plate is arranged on the dielectric layer and part of the second source field plate covers part of the first source field plate. According to an embodiment of the present invention, the dielectric layer covered by the second source field plate has a first thickness, the dielectric layer covered by the first source field plate has a second thickness, and the first thickness is smaller than the second thickness. According to an embodiment of the present invention, a portion of the second source field plate is located between the gate structure and the first source field plate. According to an embodiment of the invention, wherein the second source field plate is a titanium nitride (TiN) layer and the dielectric layer is a silicon nitride (SiN) layer. The invention further provides a method for manufacturing the high electron mobility transistor device, which comprises the steps of forming a barrier layer on the channel layer, forming a dielectric layer on the barrier layer, defining and etching the dielectric layer by using a first photomask to form a drain recess, forming a source/drain metal layer on the dielectric layer, filling the drain recess by using a second photomask to define and etch the source/drain metal layer to form a drain and a first source field plate, wherein the first source field plate is located between the drain and the gate structure, forming a second source field plate metal layer, wherein the second source field plate metal layer is arranged on the dielectric layer, the drain and the first source field plate, and defining and etching the second source field plate metal layer by using a third photomask to form a second source field plate, wherein part of the second source field plate covers part of the first source field plate. According to an embodiment of the invention, the second mask defines a distance between the drain and the first source field plate and a distance between the drain and the second source field plate. According to an embodiment of the present invention, the dielectric layer covered by the second source field plate has a first thickness, and the dielectric layer covered by the first source field plate has a second thickness, wherein the first thickness is smaller than the second thickness. According to an embodiment of the present invention, the second source