CN-122002847-A - Junction-free transistor and manufacturing method thereof

CN122002847ACN 122002847 ACN122002847 ACN 122002847ACN-122002847-A

Abstract

The application provides a junction-free transistor and a manufacturing method thereof, wherein the junction-free transistor comprises a substrate, an oxygen buried layer, a core layer, a shell layer, a grid electrode on the shell layer, source and drain electrodes positioned on two sides of the grid electrode, and a side wall positioned between the grid electrode and the source and drain electrodes, wherein the doping concentration of the shell layer is smaller than that of the core layer, the side wall of the side wall facing the grid electrode comprises a first plane, the side wall of the side wall far away from the grid electrode comprises a second plane, and a connecting surface for connecting the first plane and the second plane is arranged on one side facing the core layer, and the thickness of the side wall starts at the intersection position of the second plane and the connecting surface and is in a descending trend in the direction close to the core layer. That is, the sharp angle of one side of the side wall far away from the grid electrode is cancelled through the arrangement of the connecting surface, the blocking of the tip end of the side wall to a passage between the source electrode, the drain electrode and the channel is avoided, the series resistance of the device is reduced, the on-state current of the device is improved, and a high-performance working mode is realized.

Inventors

XU YONG
TANG ZHIYU
LI BINHONG
WANG YUN

Assignees

广东省大湾区集成电路与系统应用研究院

Dates

Publication Date: 20260508
Application Date: 20241104

Claims (10)

1. A junction-free transistor, comprising: A substrate; the substrate is sequentially laminated with an oxygen burying layer, a nuclear layer and a shell layer, wherein the doping concentration of the shell layer is smaller than that of the nuclear layer; A gate electrode on the shell layer; source and drain electrodes positioned on two sides of the grid electrode; The side wall is positioned between the grid electrode and the source drain, the side wall of the side wall facing the grid electrode comprises a first plane, the side wall of the side wall far away from the grid electrode comprises a second plane, one side facing the nuclear layer is connected with the connecting surface of the first plane and the second plane, and the thickness of the side wall starts at the intersection position of the second plane and the connecting surface and is in a descending trend in the direction close to the nuclear layer.
2. The junction-free transistor of claim 1, wherein the distance between the intersection location and the plane of the upper surface of the shell layer is in the range of 2-6nm.
3. The junction-free transistor of claim 2, wherein the distance is in the range of 2-4nm.
4. The junction-free transistor of claim 1, wherein said connection surface is an outwardly convex arcuate surface.
5. The junction-free transistor of claim 1, wherein the connection face comprises a third plane, the third plane having an angle greater than 45 ° with respect to the first plane.
6. The junction-free transistor of claim 5, wherein the third plane is connected to the first plane, the connection plane further comprising the fourth plane between the third plane and the second plane, an included angle between the third plane and the fourth plane being greater than 90 °, and an included angle between the fourth plane and the second plane being greater than 90 °.
7. The junction-free transistor of claim 1, wherein the connection face comprises a plurality of fifth planes connected in series, the first plane, the plurality of fifth planes, and the second plane forming a stepped structure.
8. The junction-free transistor of any one of claims 1-7, wherein the core layer has a thickness in the range of 3-10nm and the shell layer has a thickness in the range of 3-10nm.
9. The junction-free transistor of claim 8, wherein the core layer has a thickness in the range of 3-5nm and the shell layer has a thickness in the range of 3-5nm.
10. A method for manufacturing a junction-free transistor is characterized in that, Providing a substrate, wherein an oxygen buried layer, a core layer and a shell layer are sequentially laminated on the substrate, and the doping concentration of the shell layer is smaller than that of the core layer; The method comprises the steps of forming a grid electrode on a shell layer, forming source and drain regions on two sides of the grid electrode, and forming a side wall between the grid electrode and the source and drain regions, wherein the side wall of the side wall facing the grid electrode comprises a first plane, the side wall of the side wall far away from the grid electrode comprises a second plane, and a connecting surface connecting the first plane and the second plane on one side facing a nuclear layer, and the thickness of the side wall starts at the intersection position of the second plane and the connecting surface and is in a descending trend in the direction close to the nuclear layer.

Description

Junction-free transistor and manufacturing method thereof Technical Field The invention relates to the field of semiconductors, in particular to a junction-free transistor and a manufacturing method thereof. Background In the past half-century, CMOS technology-based integrated circuit technology has followed "moore's law," i.e., increasing the operating speed of chips, increasing integration, and reducing cost by shrinking the feature sizes of devices. As the feature size of the MOS device is continuously reduced, the distance between the source and the drain is also shorter and shorter, and the channel is not only affected by the gate electric field, but also affected by the drain electric field, so that the control capability of the gate on the channel is degraded, and this effect that the transistor performance is seriously degraded due to the reduced channel size is called a short channel effect. In order to suppress short channel effects, ultra shallow junctions must be formed in the device. Due to diffusion laws and statistical properties of dopant atom distribution in semiconductors, forming ultra-shallow junctions with high dopant concentration gradients in small-sized devices has become an increasingly difficult challenge for the semiconductor industry, which not only places extremely high demands on thermal budget, process conditions, but also greatly increases manufacturing costs. To overcome the difficulty in surmounting the MOS device at advanced process nodes, a new transistor has been developed, and Junction-less (JL) transistor does not need to be doped additionally at the Source and Drain to form a PN Junction, but rather is doped uniformly between the Source and Drain and the channel, so that JL transistor has no Junction, which is turned off by exhausting carriers in the channel, as shown in fig. 1, is a schematic structure of a current Junction-less transistor, which includes silicon nanowires (Silicon nanowire), doped uniformly with silicon nanowires, fortunately layered channel and Source (Source) and Drain (Drain) at both sides of the channel, and Gate oxide (Gate oxide) surrounding the channel and between the channel and the Gate. The junction-free transistor has the advantages of strong capability of inhibiting short channel effect, multi-threshold adjustment, low noise and the like, and the junction-free transistor is hopeful to be a powerful competitor in advanced technology node expansion process. The junction-free transistor fully depletes carriers in the channel by the work function difference between the gate material and the silicon nanowire to achieve turn-off of the junction-free transistor. Referring to fig. 2, which is a contour diagram of electron concentration of an N-type junction-free transistor, as shown in fig. 2 (a), electrons in a channel are completely consumed when the device is turned off, and no current flows through the channel. Applying a gate voltage may reduce depletion of the channel portion, forming a conductive channel between the source and drain when the device is turned on (b) in fig. 2), and current is transported in the bulk of the semiconductor. As the applied gate voltage increases, the cross-sectional area of the conductive channel increases (fig. 2 (c)), and when the gate voltage increases to a flat band voltage, the entire channel reaches a neutral condition (fig. 2 (d)), at which time current is transferred across the entire silicon nanowire, and further increases in gate voltage form an accumulation channel on the semiconductor surface. In the process manufacturing level, as the source and drain channels are uniformly doped, the high-temperature annealing activated by source and drain implantation and source and drain doping is reduced by the transistor-free process steps, and the thermal budget is obviously reduced while the process complexity is reduced. Furthermore, the junction-free transistor has advantages in 3D sequential integration, and is very suitable for realizing the manufacture of a top-layer device under low thermal budget. The application of the junction-free transistor in the prior art node also has the unique advantage that the electric field lines at the edge of the gate of the junction-free transistor can deplete part of the source and the drain, and the effective channel length can be larger than the physical gate length when the transistor is in the off state, so that the influence of short channel effect is reduced. However, junction-free transistors also suffer from the fundamental disadvantages of low mobility, negative threshold voltage, etc. Disclosure of Invention Therefore, the application aims to provide the junction-free transistor, which improves the on-state current of the device, reduces the off-state current and improves the performance of the device. The embodiment of the application provides a junction-free transistor, which comprises the following components: A substrate; the substrate is sequentially la