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CN-122002848-A - Semiconductor device and method for manufacturing the same in polycrystalline opening

CN122002848ACN 122002848 ACN122002848 ACN 122002848ACN-122002848-A

Abstract

The application discloses a semiconductor device and a manufacturing method of the semiconductor device in a polycrystalline opening, wherein the semiconductor device comprises a substrate, an epitaxial layer of a first doping type, a plurality of base electrodes, a well region, a source region, a grid electrode, a first doping buried layer, a second doping buried layer and a source metal layer, the epitaxial layer is etched with a groove, the base electrodes are arranged in the epitaxial layer, the side edges of the well region and the source region are connected with the base electrodes, the grid electrode is formed by polysilicon filled in the groove and provided with a hole, the first doping buried layer and the second doping buried layer are formed at the bottom end of the grid electrode, the first doping buried layer and the second doping buried layer are not connected with the base electrodes, the first doping buried layer is of the first doping type, the second doping buried layer is of the second doping type different from the first doping type, and the source metal layer is connected with the base electrodes and the source region and is connected with the second doping buried layer. The application can effectively solve the problem caused by charge storage/accumulation effect and make the device not easily affected by the groove, and the design window and the process window of the device can be larger.

Inventors

  • REN WEIQIANG

Assignees

  • 深圳真茂佳半导体有限公司

Dates

Publication Date
20260508
Application Date
20241108

Claims (10)

  1. 1. A semiconductor device, comprising: A substrate (10); An epitaxial layer (20) of a first doping type formed on the upper surface of the substrate (10), the epitaxial layer (20) being etched with a trench (21); A plurality of bases (30) of a second doping type, disposed within the epitaxial layer (20); A well region and a source region (42) disposed within the epitaxial layer (20), the sides of the well region and the source region (42) being in contact with the base (30); a gate (70) formed of polysilicon filled in the trench (21), the bottom end of the gate (70) penetrating through the well region and the source region (42), the polysilicon having a hole (71); A first doped buried layer (50) and a second doped buried layer (51) formed at the bottom end of the gate (70), wherein the first doped buried layer (50) and the second doped buried layer (51) are not connected to the base (30), the first doped buried layer (50) is of a first doping type, and the second doped buried layer (51) is of a second doping type different from the first doping type; And a source metal layer (80) formed on the upper surface of the epitaxial layer (20) to connect the base (30) and the source region (42), wherein the source metal layer (80) is further formed in the hole (71) so that the source metal layer (80) penetrates through the well region and the source region (42) and is connected to the second doped buried layer (51).
  2. 2. A semiconductor device according to claim 1, wherein the hole (71) is formed by cutting off polysilicon in a lateral direction and not cutting off polysilicon in a longitudinal direction so that the hole (71) has a first window shape.
  3. 3. A semiconductor device according to claim 1, wherein said cutouts (71) do not cut off polysilicon in both the lateral and longitudinal directions so that the cutouts (71) are in the shape of a second window, and a plurality of groups of said cutouts (71) in said polysilicon are arranged in parallel in the lateral direction.
  4. 4. A semiconductor device according to claim 1, wherein said cutouts (71) do not cut off polysilicon in both the lateral and longitudinal directions so that the cutouts (71) are in the shape of a second window, and a plurality of groups of said cutouts (71) in said polysilicon are staggered in the lateral direction.
  5. 5. A semiconductor device according to claim 1, wherein the hole (71) is formed by cutting the polysilicon in a lateral direction and cutting the polysilicon in a longitudinal direction so that the hole (71) has a long groove shape.
  6. 6. A semiconductor device according to claim 1, characterized in that the well region comprises a first conductive channel region (40) and a second conductive channel region (41) arranged from bottom to top, the first conductive channel region (40) being of a first doping type, the second conductive channel region (41) being of a second doping type, the source region (42) being of the first doping type; Wherein the doping concentration of the base (30) is higher than the doping concentration of the first conductive channel region (40) and the doping concentration of the second conductive channel region (41) is lower than the doping concentration of the source region (42), the second conductive channel region (41) constituting an internal negative feedback resistance between the first conductive channel region (40) and the source region (42).
  7. 7. The semiconductor device according to claim 1, further comprising an insulating layer (72), wherein the insulating layer (72) is disposed between the epitaxial layer (20) and the source metal layer (80), and further comprising a passivation layer (81) disposed on an upper surface of the source metal layer (80), wherein a resin layer (82) is disposed on an upper surface of the passivation layer (81), wherein the passivation layer (81) has a thickness of 0.1um to 20um, and wherein the resin layer (82) has a thickness of 1um to 50um.
  8. 8. A method of manufacturing a semiconductor device in a poly-crystalline opening for use in manufacturing a semiconductor device as claimed in any one of claims 1-7, comprising the steps of: S10, providing a substrate (10), wherein an epitaxial layer (20) of a first doping type is formed on the upper surface of the substrate (10); S20, implanting ions into the epitaxial layer (20) for the first time to form a plurality of base electrodes (30) with a second doping type in the epitaxial layer (20); S30, implanting ions into the epitaxial layer (20) for the second time to form a well region and a source region (42) in the epitaxial layer (20), wherein the sides of the well region and the source region (42) are connected with the base electrode (30); S40, etching the epitaxial layer (20) to form a groove (21) penetrating the well region and the source region (42), wherein the groove (21) is not connected with the base electrode (30); S50, implanting ions into the epitaxial layer (20) for the third time to sequentially form a first doped buried layer (50) and a second doped buried layer (51) at the bottom of the groove (21), wherein the first doped buried layer (50) is of a first doping type, the second doped buried layer (51) is of a second doping type different from the first doping type, and the first doped buried layer (50) and the second doped buried layer (51) are not connected to the base electrode (30); s60, depositing polycrystalline silicon into the groove (21) to form a grid electrode (70), wherein the polycrystalline silicon is provided with a hole (71); And S70, forming a source metal layer (80) on the upper surface of the epitaxial layer (20) so as to connect the base electrode (30) and the source electrode region (42), wherein the source metal layer (80) is also formed in the hole (71) of the polysilicon, so that the source metal layer (80) is connected to the second doped buried layer (51) through the well region and the source electrode region (42).
  9. 9. The method of manufacturing a semiconductor device in a poly-opening according to claim 8, wherein step S60 comprises: S61, cutting off the polysilicon along the transverse direction and continuously cutting off the polysilicon along the longitudinal direction to form a first window-shaped hole (71), or, S61, continuously digging the polysilicon along the transverse direction and the longitudinal direction to form second window-shaped digging holes (71), wherein a plurality of groups of digging holes (71) in the polysilicon are arranged in parallel along the transverse direction, or, S61, continuously digging the polysilicon along the transverse direction and the longitudinal direction to form second window-shaped digging holes (71), wherein a plurality of groups of digging holes (71) in the polysilicon are arranged in a staggered way along the transverse direction, or, S61, the polysilicon is not cut off along the transverse direction, and the polysilicon is cut off along the longitudinal direction to form a long groove-shaped hole (71).
  10. 10. The method of manufacturing a semiconductor device in a poly-opening according to claim 8, wherein step S30 comprises: s31, implanting ions into the epitaxial layer (20) to form a first conductive channel region (40) with a second doping type; S32, implanting ions into the epitaxial layer (20) to form a second conductive channel region (41) with a first doping type, wherein the first conductive channel region (40) and the second conductive channel region (41) are combined to form a well region; S33, implanting ions into the epitaxial layer (20) to form a source region (42) of a first doping type; The doping concentration of the base electrode (30) is higher than that of the first conductive channel region (40), and the doping concentration of the second conductive channel region (41) is lower than that of the source region (42), so that an internal negative feedback resistor between the first conductive channel region (40) and the source region (42) is formed, and gate-source voltage withstand and partial pressure are achieved.

Description

Semiconductor device and method for manufacturing the same in polycrystalline opening Technical Field The present application relates to the field of semiconductor power devices, and more particularly, to a semiconductor device and a method for manufacturing the same in a polycrystalline opening. Background TrenchMosfet (trench mosfet), which is a transistor structure, is an advanced technology developed on the basis of conventional PlanarMosfet (planar mosfet). The TrenchMOS technology achieves higher integration and better electrical performance by etching deep trenches in the surface of the semiconductor material and forming transistors on the sidewalls of the trenches. TrenchMosfet the gate is buried in the substrate to form a vertical channel, the area occupied by the gate is reduced compared with PlanarMosfet, the cell size (CELLPITCH) can be made smaller, the area occupied by the chip through which current flows is increased, and the area of the chip is more fully utilized. And the same chip area and the smaller cell size can be used for connecting more cells in parallel, so that the unit density of a unit cell and a channel is improved, and the on-resistance is reduced. Trenchmosfet gate width is much smaller than planar structure, parasitic gate drain capacitance Cgd, i.e., reverse transfer capacitance (miller capacitance) is greatly reduced, and switching losses are greatly reduced. However, under the high drain voltage, a large electric field exists at the bottom of the trench, which is easy to break down, and the voltage resistance and reliability of the device are affected. Disclosure of Invention In order to improve the compression resistance of the device and prolong the service life of the device, the application provides a semiconductor device and a manufacturing method thereof in a polycrystalline opening. The first aspect of the present application provides a semiconductor device, which adopts the following technical scheme: a semiconductor device, comprising: A substrate; An epitaxial layer of a first doping type is formed on the upper surface of the substrate, and a groove is etched in the epitaxial layer; a plurality of bases of a second doping type disposed within the epitaxial layer; The well region and the source region are arranged in the epitaxial layer, and the sides of the well region and the source region are connected with the base electrode; The grid electrode is formed by polysilicon filled in the groove, the bottom end of the grid electrode penetrates through the well region and the source electrode region, and the polysilicon is provided with a hole; The first doped buried layer and the second doped buried layer are formed at the bottom end of the grid electrode, the first doped buried layer and the second doped buried layer are not connected to the base electrode, the first doped buried layer is of a first doping type, and the second doped buried layer is of a second doping type different from the first doping type; And the source electrode metal layer is formed on the upper surface of the epitaxial layer so as to connect the base electrode and the source electrode region, and is also formed in the hole so that the source electrode metal layer penetrates through the well region and the source electrode region and is connected to the second doped buried layer. By adopting the technical scheme, the P-type and N-type regions at the bottom of the groove with a unique structure are formed, the on-resistance of the device is effectively reduced, and the voltage-withstanding capability and reliability of the device are improved. The application can effectively solve the problem caused by charge storage/accumulation effect by grounding the second doped buried layer, meanwhile, the performance of switching on and off of the device is influenced by the depth and the appearance of the groove only by injecting at the bottom of the groove, and the device is not easily influenced by the groove by injecting base electrodes at two sides of the first doped buried layer and the second doped buried layer, so that the design window and the process window of the device can be larger. Optionally, the hole digs the polysilicon along the transverse direction, and the polysilicon is not dug along the longitudinal direction so that the hole digs takes the shape of a first window. By adopting the technical scheme, the polysilicon grid is excavated transversely and continuously in the longitudinal direction, so that a first window-shaped hole is formed. The design can effectively reduce the parasitic capacitance of the polysilicon gate, especially the parasitic capacitance between the gate and the source, thereby reducing the switching loss and improving the switching speed of the device. Meanwhile, the electric field distribution of the grid electrode can be improved through the hole digging design, and the reliability and the compression resistance of the device are further improved. Optionally, t