CN-122002849-A - Vertical annular channel three-dimensional transistor and preparation method thereof

CN122002849ACN 122002849 ACN122002849 ACN 122002849ACN-122002849-A

Abstract

The invention relates to a vertical annular channel three-dimensional transistor and a preparation method thereof, wherein the vertical annular channel three-dimensional transistor comprises M stacked layers, wherein M is a positive integer, and each stacked layer comprises a silicon nitride layer, a first doped polysilicon layer, an oxide layer and a second doped polysilicon layer which are sequentially deposited; a gate structure, wherein the gate structure comprises a gate electrode, and a channel region and a gate oxide corresponding to each of the stacked layers; M sources and M drains formed based on contact steps formed on the M stacked layers using a step process. Through the scheme, the density and the integration level of the transistor are improved, and the capacity of the transistor is improved, so that the processing capacity of the transistor is improved.

Inventors

ZHANG JIANPING
ZHU ZHENGPENG
WANG HAOTONG

Assignees

成都新紫光半导体科技有限公司

Dates

Publication Date: 20260508
Application Date: 20241108

Claims (10)

1. A vertical ring channel three-dimensional transistor, comprising: M stacking layers, wherein M is a positive integer, and each stacking layer comprises a silicon nitride layer, a first doped polysilicon layer, an oxide layer and a second doped polysilicon layer which are sequentially deposited; A gate structure, wherein the gate structure comprises a gate electrode and a channel region and a gate oxide corresponding to each of the stacked layers; m sources and M drains formed based on contact steps formed on the M stacked layers using a step process.
2. The vertical ring channel three-dimensional transistor according to claim 1, wherein in the case where M is a positive integer greater than 1, the M stacked layers are vertically stacked in order.
3. The vertical ring channel three-dimensional transistor according to claim 1, wherein for each of the stacked layers, the source and the drain of the stacked layer are respectively connected to different doped polysilicon layers in the stacked layers.
4. The vertical ring channel three-dimensional transistor of claim 1, wherein the gate electrode extends vertically through the M stacked layers, and wherein the gate electrode is of a phosphorus doped polysilicon.
5. The vertical ring channel three-dimensional transistor according to claim 1, wherein the channel region corresponding to the stacked layer is formed by depositing boron doped polysilicon or phosphorus doped polysilicon in two oxide recesses, which are two recesses in a horizontal direction etched on an oxide layer in the stacked layer, the two oxide recesses corresponding to both sides of the gate electrode.
6. The vertical ring channel three-dimensional transistor according to claim 1, wherein the gate oxide corresponding to the stacked layer is formed on both sides of the gate electrode at positions corresponding to the first doped polysilicon layer, the oxide layer, and the second doped polysilicon layer in the stacked layer.
7. A method for fabricating a vertical ring channel three-dimensional transistor, wherein the method is used to fabricate the vertical ring channel three-dimensional transistor of any of claims 1-6, the method comprising: Forming M stacking layers, wherein M is a positive integer, and each stacking layer comprises a silicon nitride layer, a first doped polysilicon layer, an oxide layer and a second doped polysilicon layer which are sequentially deposited; Etching based on the M stacking layers by utilizing photoetching and etching processes to form channel holes penetrating through the M stacking layers in the vertical direction; Forming a gate structure of the vertical annular channel three-dimensional transistor based on the channel hole, wherein the gate structure comprises a gate electrode and a channel region and a gate oxide corresponding to each stacked layer respectively; forming contact steps on the M stacked layers using a step process; And forming a source electrode and a drain electrode corresponding to each stacked layer respectively based on the contact step by utilizing a back-end process, wherein the source electrode and the drain electrode corresponding to the stacked layers are respectively connected to different doped polysilicon layers in the stacked layers.
8. The method of claim 7, wherein, in the case where M is a positive integer greater than 1, the forming M stacked layers comprises: and repeatedly performing the steps of sequentially depositing the silicon nitride layer, the first doped polysilicon layer, the oxide layer and the second doped polysilicon layer until the M stacking layers vertically stacked are formed.
9. The method of claim 7, wherein forming the gate structure of the vertical ring channel three-dimensional transistor based on the channel hole comprises: Etching two oxide grooves in the horizontal direction on the oxide layers by adopting a wet oxide etching process aiming at the oxide layers in each stacking layer to form a channel, wherein the two oxide grooves correspond to two sides of the channel hole; Depositing boron doped polysilicon or phosphorus doped polysilicon in each channel by adopting a low-pressure chemical vapor deposition method; removing the boron doped polysilicon or the phosphorus doped polysilicon deposited at other positions outside the oxide groove by adopting a wet polysilicon etching process so as to form the channel region corresponding to each stacking layer respectively; For each stacked layer, adopting an atomic layer deposition technology to deposit the grid oxide at the two sides of the channel hole and at the positions corresponding to the first doped polysilicon layer, the oxide layer and the second doped polysilicon layer of the stacked layer; And depositing phosphorus doped polysilicon in the channel holes by adopting a low-pressure chemical vapor deposition method to form a gate electrode.
10. The method of claim 7, wherein forming a respective source and drain for each of the stacked layers based on the contact step comprises: depositing a silicon nitride layer as an oxide etch stop layer on the contact step; Photoetching and etching a source contact hole and a drain contact hole corresponding to the stacked layers based on the contact steps by utilizing the back-end process; and depositing metal tungsten in the source electrode contact hole and the drain electrode contact hole, forming the source electrode and the drain electrode corresponding to each stacked layer respectively, and removing the metal tungsten on the top of the silicon nitride layer deposited on the contact step by adopting a Chemical Mechanical Planarization (CMP).

Description

Vertical annular channel three-dimensional transistor and preparation method thereof Technical Field The disclosure relates to the technical field of semiconductors, in particular to a vertical annular channel three-dimensional transistor and a preparation method thereof. Background In the field of semiconductor manufacturing, the device architecture in a Chip is being changed from 2D to 3D,3D homogeneous integration (Homogeneous Integration) and 3D heterogeneous integration (Heterogeneous Integration) are called active Chip research directions, and how to simultaneously improve the performance of a System on Chip (SoC) and a Memory Chip (Memory) under the condition of shrinking the whole area of the Chip, such as the performance of Chip processing speed, bandwidth, capacity, power consumption and the like, is a problem to be solved. Disclosure of Invention The purpose of the present disclosure is to provide a vertical ring channel three-dimensional transistor and a manufacturing method thereof, which can improve the density and performance of the transistor. To achieve the above object, in a first aspect, the present disclosure provides a vertical ring channel three-dimensional transistor, comprising: M stacking layers, wherein M is a positive integer, and each stacking layer comprises a silicon nitride layer, a first doped polysilicon layer, an oxide layer and a second doped polysilicon layer which are sequentially deposited; A gate structure, wherein the gate structure comprises a gate electrode and a channel region and a gate oxide corresponding to each of the stacked layers; m sources and M drains formed based on contact steps formed on the M stacked layers using a step process. Alternatively, in the case where M is a positive integer greater than 1, the M stacked layers are vertically stacked in order. Optionally, for each of the stacked layers, the source and the drain corresponding to the stacked layers are respectively connected to different doped polysilicon layers in the stacked layers. Optionally, the gate electrode penetrates through the M stacked layers in a vertical direction, and the material of the gate electrode is phosphorus doped polysilicon. Optionally, the channel region corresponding to the stacked layer is formed by depositing boron doped polysilicon or phosphorus doped polysilicon in two oxide grooves, wherein the two oxide grooves are two grooves in a horizontal direction formed by etching on an oxide layer in the stacked layer, and the two oxide grooves correspond to two sides of the gate electrode. Optionally, the gate oxide corresponding to the stacked layer is formed on both sides of the gate electrode and at positions corresponding to the first doped polysilicon layer, the oxide layer and the second doped polysilicon layer in the stacked layer. In a second aspect, the present disclosure provides a method for preparing a vertical ring channel three-dimensional transistor, the method being used for preparing the vertical ring channel three-dimensional transistor provided in the first aspect of the present disclosure, the method comprising: Forming M stacking layers, wherein M is a positive integer, and each stacking layer comprises a silicon nitride layer, a first doped polysilicon layer, an oxide layer and a second doped polysilicon layer which are sequentially deposited; Etching based on the M stacking layers by utilizing photoetching and etching processes to form channel holes penetrating through the M stacking layers in the vertical direction; Forming a gate structure of the vertical annular channel three-dimensional transistor based on the channel hole, wherein the gate structure comprises a gate electrode and a channel region and a gate oxide corresponding to each stacked layer respectively; forming contact steps on the M stacked layers using a step process; And forming a source electrode and a drain electrode corresponding to each stacked layer respectively based on the contact step by utilizing a back-end process, wherein the source electrode and the drain electrode corresponding to the stacked layers are respectively connected to different doped polysilicon layers in the stacked layers. Optionally, in the case where M is a positive integer greater than 1, the forming the M stacked layers includes: and repeatedly performing the steps of sequentially depositing the silicon nitride layer, the first doped polysilicon layer, the oxide layer and the second doped polysilicon layer until the M stacking layers vertically stacked are formed. Optionally, the forming the gate structure of the vertical ring channel three-dimensional transistor based on the channel hole includes: Etching two oxide grooves in the horizontal direction on the oxide layers by adopting a wet oxide etching process aiming at the oxide layers in each stacking layer to form a channel, wherein the two oxide grooves correspond to two sides of the channel hole; Depositing boron doped polysilicon or phosphorus do