CN-122002850-A - Semiconductor device and method for manufacturing the same

Abstract

The application discloses a semiconductor device and a method of manufacturing the same. The semiconductor device includes a support substrate, and a channel layer parallel to a top surface of the support substrate, extending along a first direction, and sequentially including a drain, a channel, and a source along the first direction. A top surface of the channel deviates less than three times its root mean square roughness.

Inventors

• CAI ZHENYU

Assignees

• 南亚科技股份有限公司

Dates

Publication Date

20260508

Application Date

20250422

Priority Date

20241108

Claims (20)

1. 1. A semiconductor device, comprising: a supporting substrate, and A channel layer positioned parallel to a top surface of the support substrate, extending along a first direction, and sequentially comprising a drain electrode, a channel and a source electrode along the first direction, Wherein a top surface of the channel deviates less than three times its root mean square roughness.
2. 2. The semiconductor device of claim 1, further comprising a word line structure positioned parallel to the top surface of the support substrate, extending along a second direction perpendicular to the first direction, and surrounding the channel.
3. 3. The semiconductor device of claim 2, wherein said word line structure comprises a word line dielectric layer surrounding said channel and a word line conductive layer surrounding said word line dielectric layer.
4. 4. The semiconductor device of claim 3, further comprising a storage node structure contacting said drain.
5. 5. The semiconductor device of claim 4, further comprising a bit line contacting said source.
6. 6. The semiconductor device of claim 5, further comprising a plurality of interfacial insulation layers covering the source and drain electrodes, respectively.
7. 7. The semiconductor device of claim 6, wherein a thickness of said word line dielectric layer and a thickness of said plurality of interfacial insulating layers are substantially the same.
8. 8. The semiconductor device of claim 6, wherein a thickness of said word line dielectric layer and a thickness of said plurality of interfacial insulating layers are different.
9. 9. The semiconductor device of claim 6, further comprising a wordline cover layer covering said wordline structure.
10. 10. The semiconductor device of claim 9, wherein a top surface of the wordline cladding layer and a top surface of the bitline are substantially coplanar.
11. 11. The semiconductor device of claim 10, further comprising a node overlay positioned between said word line overlay and said storage node structure.
12. 12. The semiconductor device of claim 11, further comprising a channel fill dielectric layer positioned between said plurality of interfacial insulating layers and said wordline cover layer.
13. 13. The semiconductor device of claim 12, wherein a top surface of the channel fill dielectric layer and a top surface of the node cap layer are substantially coplanar.
14. 14. The semiconductor device of claim 13, wherein said plurality of interface insulating layers and said word line dielectric layer comprise the same material.
15. 15. The semiconductor device of claim 13, wherein said plurality of interface insulating layers and said word line dielectric layer comprise different materials.
16. 16. A method of manufacturing a semiconductor device, comprising: providing a supporting substrate; Forming a channel layer parallel to a top surface of the support substrate, extending along a first direction, and sequentially including a drain electrode, a channel and a source electrode along the first direction; Conformally forming an interface insulating layer covering the channel layer, and Performing a first heat treatment on the channel layer and the interface insulating layer, Wherein a top surface of the channel layer deviates less than three times its root mean square roughness.
17. 17. The method for manufacturing a semiconductor device according to claim 16, wherein the first heat treatment is performed at a temperature higher than 1000 ℃.
18. 18. The method of manufacturing a semiconductor device according to claim 16, wherein the first heat treatment is performed in a non-oxidizing atmosphere.
19. 19. The method of manufacturing a semiconductor device of claim 18, wherein the non-oxidizing ambient comprises argon, nitrogen, hydrogen, or a combination thereof.
20. 20. The method of claim 16, wherein said first thermal treatment is a rapid thermal annealing process.

Description

Semiconductor device and method for manufacturing the same Technical Field The priority of U.S. patent application Ser. No. 18/941,106 (i.e., priority date "day 11 of 2024"), the contents of which are incorporated herein by reference in their entirety, is claimed. The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device having a horizontal channel layer and a method of manufacturing a semiconductor device having a horizontal channel layer. Background Semiconductor devices are used in a variety of electronic applications such as personal computers, cellular phones, digital cameras, and other electronic equipment. Semiconductor devices are continually shrinking in size to meet the increasing demands for computing power. However, various problems occur in the shrinking process, and these problems are increasing. Thus, challenges remain in terms of improving quality, yield, performance, and reliability, and reducing complexity. The above description of "prior art" is provided merely as background, and is not admitted to disclose the subject matter of the present disclosure, do not constitute prior art to the present disclosure, and any description of "prior art" above should not be taken as any part of the present disclosure. Disclosure of Invention An embodiment of the present disclosure provides a semiconductor device including a support substrate, and a channel layer parallel to a top surface of the support substrate, extending along a first direction, and sequentially including a drain, a channel, and a source along the first direction. A top surface of the channel deviates less than three times its root mean square roughness. Another embodiment of the present disclosure provides a method of manufacturing a semiconductor device, including providing a support substrate, forming a channel layer parallel to a top surface of the support substrate, extending along a first direction and sequentially including a drain electrode, a channel and a source electrode along the first direction, conformally forming an interface insulating layer covering the channel layer, and performing a first heat treatment on the channel layer and the interface insulating layer. A top surface of the channel layer deviates less than three times its root mean square roughness. Another embodiment of the present disclosure provides a method of manufacturing a semiconductor device, including providing a support substrate, forming a channel layer parallel to a top surface of the support substrate, extending along a first direction and sequentially including a drain electrode, a channel and a source electrode along the first direction, conformally forming a word line dielectric layer covering the channel of the channel layer, and performing a second heat treatment on the channel layer and the word line dielectric layer. A top surface of the channel deviates less than three times its root mean square roughness. Due to the design of the semiconductor device of the present disclosure, by employing the heat treatment, the surface roughness (or interface roughness) of the channel layer can be improved, and the stress of the channel layer can be reduced. Accordingly, the performance of the semiconductor device can be improved. In addition, by employing a thicker word line dielectric layer consisting of an inner word line dielectric layer and an outer word line dielectric layer, gate induced drain leakage can be reduced. Thus, the performance (e.g., retention time) of the semiconductor device can be improved. In addition, the external word line dielectric layer comprising a high-k dielectric material may improve the drain current of the semiconductor device. The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Other technical features and advantages that form the subject of the claims of the present disclosure are described below. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims. Drawings The disclosure of the present application may be more fully understood when the detailed description and claims are taken together with the accompanying drawings, in which like reference numerals refer to like elements. Fig. 1 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 2 is a schematic view illustrating a top view of an intermediate semiconductor device acc